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UPD360 Datasheet(PDF) 65 Page - Microchip Technology |
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UPD360 Datasheet(HTML) 65 Page - Microchip Technology |
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65 / 221 page ![]() 2016-2017 Microchip Technology Inc. DS00002084C-page 65 UPD360 8.5.40 VOLTAGE REGULATOR CONTROL REGISTER (VREG_CTL) 8.5.41 I2C TRIM REGISTER (I2C_TRIM) 8.5.42 GENERAL PURPOSE TIMER LOAD REGISTER (GP_TIMER_LOAD) Address: 009Ch Size: 8 bits Bits Description Type Default 7:1 RESERVED RO - 1 VREG_LOW_OVR When set, the 1.8V voltage regulator is placed in low power mode whenever both the Ring Oscillator and 48MHz Relaxation Oscillator are disabled. Note: It is expected tor this bit to be set in CPU companion mode. Note: In standalone modes, the respective OTP bit shall be set to enable this feature and to ensure maximum power savings. R/W 0b 0 VREG Low Power Enable (VREG_LOW_EN) When set, the 1.8V voltage regulator is placed in low power mode. Note: This bit has no meaning when the VREG_LOW_OVR bit is set. R/W 0b Address: 009Dh Size: 8 bits BITS DESCRIPTION TYPE DEFAULT 7:0 I2C_TRIM This register specifies the delay added by the I2C controller in order to meet the tHD_DAT parameter. This register has units of 20.8 ns. R/W 9h Address: 00A0h Size: 16 bits BITS DESCRIPTION TYPE DEFAULT 15:0 GP Timer Load This register defines the value to be loaded into the general purpose timer from which it will count down. The valid range for this register is 0001h - FFFFh. This field has units of 1 ms. Note: Programming 0h into this register is not valid. Note: Software shall not change the contents of this register while the RESET bit is set and shall wait until this bit is cleared. R/W FFFFh |
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