UPD360 datasheet(35/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 35

UPD360

8.0

SYSTEM CONTROL

This section details the following system controls:

• System Interrupts

• General Purpose I/O

• External Over-current Detection

• System Control Registers

8.1

System Interrupts

The device provides an open drain interrupt pin, IRQ_N, which is asserted as a function of the System Control’s Interrupt

Status Register (INT_STS) and Interrupt Enable Register (INT_EN). The following interrupts are supported:

• HPD Interrupt

• Power Switch Module Interrupt

• Watchdog Timer Assertion Interrupt

• Port Power Controller Interrupt

• Power Delivery MAC Interrupt

• OCS Comparator Interrupt

• PIO Override Interrupt

• PIO Interrupt

• CC Interrupt

• VBUS Interrupt

• Power Control Interrupt

• Device Ready Interrupt

In order to clear an interrupt status bit, the source of the asserted bit in Interrupt Status Register (INT_STS) must be

cleared. This process typically involves dealing with the module (e.g. PD MAC, CC, Port Power Controller, Watchdog

Timer, Power Switch, etc.) that triggered the interrupt or configuring the respective module’s interrupt enable register to

disable assertion.

The PIO interrupts are cleared by writing “1” to the asserted bit(s) in PIO Interrupt Status Register (PIO_INT_STS). The

PIO Override interrupts are cleared by writing “1” to the asserted bit(s) in PIO Override Interrupt Status Register

(PIO_OVR_INT_STS). The OCS interrupts are cleared by is cleared by writing “1” to the asserted bit(s) in OCS Com-

parator Change Status Register (OCS_CMP_CHG_STS).

Figure 8-1 illustrates the device’s interrupt hierarchy. Figure 8-2 illustrates the generation of the CC_INT bit in the Inter-

rupt Status Register (INT_STS).

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