UPD360 datasheet(26/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 26

 2016-2017 Microchip Technology Inc.

6.0

SPI SLAVE CONTROLLER (UPD360-C ONLY)

This chapter details the integrated SPI slave controller (SPI_DI, SPI_DO, SPI_CLK, and SPI_CS) available in the

UPD360-C. The SPI slave controller can be used for Host CPU serial management and data transfer, and allows host

access to all device Configuration and Status Registers (Section 4.0, "Register Map," on page 19).

6.1

SPI Overview

The SPI Slave module provides a low pin count synchronous slave interface that facilitates communication between the

device and a host system. The SPI slave allows access to the System CSRs and internal FIFOs and memories. It sup-

ports single and multiple register read and write commands with incrementing, decrementing and static addressing.

Only a Single bit lane is supported in SPI mode at up to 25 MHz.

The following is an overview of the functions provided by the SPI Slave:

• Fast Read: 4-wire (clock, select, data in and data out) reads. Serial command, address and data. This is called

“Fast” Read for historical reasons, and is the only Read command supported. There is a single Dummy byte

required for first access. Single and multiple register reads with incrementing, decrementing or static addressing.

• Write: 4-wire (clock, select, data in and data out) writes at up to 25 MHz. Serial command, address and data. Sin-

gle and multiple register writes with incrementing, decrementing or static addressing.

6.2

SPI Slave Operation

A SPI frame starts on the falling edge of SPI_CS, and ends with SPI_CS rising. At the edges of SPI_CS, the SPI_CLK

clock may be at its reset state of either low (Mode 0) or high (Mode 3), at the option of the Master.

Input data on the SPI_DI pin (often called “MOSI”) is sampled on the rising edge of the SPI_CLK input clock. Output

data is launched on the SPI_DO pin (often called “MISO”) with the falling edge of the clock. While the SPI_CS chip select

input is high, the SPI_DI and SPI_CLK inputs are ignored and the SPI_DO output is floating.

Each frame starts with an 8-bit instruction byte, transmitted by the Master, and it is accepted on SPI_DI starting at the

first rising edge of the input clock after SPI_CS goes active.

For both Write and (Fast) Read instructions, two address bytes follow the instruction byte. The address field expresses

a byte address. Fourteen address bits specify the address. The remaining two bits [15:14] constitute the DIR subfield

of the address field, which specifies whether the address is Auto-Incremented (00b) or Auto-Decremented (10b) for con-

secutive data bytes in the frame. A special Static address coding (11b) keeps the address static throughout the frame

of data, causing a single byte address to be accessed repeatedly if multiple bytes are transferred in the frame. DIR sub-

field encoding 01b is reserved and should be decoded in implementation to be the same as 00b, for the sake of mini-

mizing the effect of a software error that increments beyond the address space.

For the Fast Read instruction, one dummy byte follows the address bytes. The dummy byte occupies 8 bits, one per

clock.

The device will normally not drive SPI_DO during the Instruction, Address or Dummy byte cycles, but see Section 6.2.2,

"Access During and Following Power Management," on page 27 for a special case.

For Fast Read instructions, one or more 8-bit data fields follow the dummy byte. For Write instructions, they immediately

follow the address bytes.

Individual bytes in instruction, address and data fields are transferred with the most-significant bit (msb) first. The two-

byte Address field is transferred with the most-significant byte (MSB) first. Multi-byte data values are transferred in the

order specified by the DIR subfield of the Address field (bits [15:14]), and so their order can be effectively selected by

using Increment mode (starting from the lowest byte address) or Decrement mode (starting from the highest byte

address).

The SPI interface supports a minimum time of 50ns between successive commands (a minimum SPI_CS inactive time

of 50ns).

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