UPD360 datasheet(45/221 Pages) MICROCHIP

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 2016-2017 Microchip Technology Inc.

DS00002084C-page 45

UPD360

8.5.7

INTERRUPT STATUS REGISTER (INT_STS)

Address:

0010h

Size:

16 bits

Bits

Description

Type

Default

RESERVED

GP_TIMER_INT

Interrupt generated when the general purpose timer underflows.

This interrupt reflect that value of the GP_UFLOW bit of the General Purpose

Timer Interrupt Source Register (GP_TIMER_INT_SRC).

RESERVED

RDY_INT

Interrupt generated when the device is configured and ready for access by

host CPU after a system level reset event.

This interrupt reflect that value of the DEV_READY bit of the Hardware Con-

trol Register (HW_CTL).

RESERVED

PWR_INT

Interrupt generated power event.

This interrupt is cleared via the Power Interrupt Status Register

(PWR_INT_STS).

VBUS_INT

Indicates that a change occurred in the state of VBUS Change Status Register

(VBUS_CHG_STS).

HPD_INT

Interrupt generated by the HPD detection logic.

This interrupt is cleared via the HPD Interrupt Status Register

(HPD_INT_STS).

PSW_INT

Interrupt generated by the power switch.

This interrupt is cleared via the Power Switch Interrupt Status Register

(PWR_INT_STS).

WDT_INT

Interrupt generated by watchdog timer expiration.

This interrupt is cleared via WDT_STS bit in the Watchdog Control Register

(WDT_CTL).

Note:

When a Watchdog interrupt is pending, all write operations are

blocked until the WDT_STS bit in the Watchdog Control Register

(WDT_CTL) is cleared.

PPC_INT

Interrupt generated by PPC.

This interrupt is cleared via the PPC Interrupt Status Register 1

(PPC_INT_STS1).

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