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UPD360 Datasheet(PDF) 64 Page - Microchip Technology |
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UPD360 Datasheet(HTML) 64 Page - Microchip Technology |
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64 / 221 page ![]() UPD360 DS00002084C-page 64 2016-2017 Microchip Technology Inc. 8.5.37 OCS COMPARATOR X THRESHOLD REGISTERS (OCS_CMPX_THR) 8.5.38 OCS COMPARATOR DEBOUNCE REGISTER (OCS_CMP_DEBOUNCE) 8.5.39 IRQ_N PU/PD CONTROL REGISTER (IRQ_PUPD) This register controls the PU and PU for the IRQ_N pin. Address: x=1: 0084h x=2: 0086h Size: 16 bits Bits Description Type Default 15:10 RESERVED RO 0h 9:0 OCS Comparator Threshold The lower byte of the threshold must be written before the upper byte. The entire 10-bit threshold is updated when the second write occurs. This has units of ~2.5V/1024. Note: This register shall not be modified while the OCS debouncer is enabled. R/W 0h Address: 0088h Size: 8 bits Bits Description Type Default 7:0 OCS_CMP_DEBOUNCE Indicates the period of time for which the OCS_COMP1 and OCS_COMP2 inputs are debounced. This field has units of 100 us. Note: This register shall not be modified while the OCS debouncer is enabled. R/W 0Fh Address: 009Bh Size: 8 bits Bits Description Type Default 7 PullUpEnable 0: No pull-up 1: Pull-up enabled. R/W 0b 6 PullDownEnable 0: No pull-down 1: Pull-down enabled. R/W 0b 5:0 RESERVED RO - |
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