UPD360 datasheet(23/221 Pages) MICROCHIP

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DS00002084C-page 23

UPD360

5.2.5

ACCESS DURING AND FOLLOWING POWER MANAGEMENT

During low-power modes, a Start condition will trigger the device to wake, and the device will also stretch the I2C clock

low until its internal clocks are running and locked. It will then release the I2C clock, and process the incoming packet.

It performs these steps before receiving the Slave Address bits, meaning that if there are multiple devices of this type

asleep on the same I2C bus segment then they will all stretch the clock, and they will all wake, regardless of whether

they were actually addressed. In the event that the slave address of the I2C transaction does not match the value spec-

ified in the I2C Slave Address Register (I2C_ADDR) (UPD360-A/UPD360-B Only), the device will power-down automat-

ically.

5.2.6

I2C SLAVE READ SEQUENCE

Following the device addressing, as detailed in Section 5.2.1, a register is read from the device when the master sends

a Start condition and Control byte with the R/~W bit set to ‘1’. Assuming the slave address in the Control byte matches

the device address, the Control byte is acknowledged by the device. Otherwise, the entire sequence is ignored until the

next Start condition. Following the acknowledge, the device sends 1 or more bytes of data, from successive register

addresses according to the last-issued DIR address subfield (Section 5.2.2), until the master sends a no-acknowledge

followed by the Stop condition. The no-acknowledge informs the device not to send any further bytes.

The internal register address is unchanged if only a single register byte is read, otherwise (a Multiple Register Read)

the internal register address may be incremented or decremented (Section 5.2.2) after each byte including the final one.

If the internal address reaches its maximum, it rolls over to 0.

If the master sends an unexpected start or stop condition, the device will stop sending immediately and will respond to

the next sequence as needed.

Figure 5-4 illustrates a typical single and multiple register read. An optional Write of an address is allowed to occur first,

shown in gray. Note that this example shows an abbreviated case, where the Write does not have a Stop condition

before the Read transfer’s Starts. in this case, the Stop is still allowed, but not required.

5.2.7

I2C SLAVE WRITE SEQUENCE

Following the device addressing, as detailed in Section 5.2.1, a register value is written to the device when the master

continues to send data bytes. Each byte is acknowledged by the device. Following any data byte, after the acknowledge,

the master may either send another start condition or halt the sequence with a stop condition. The internal register

address is unchanged following a single-byte write.

Multiple writes are performed when the master sends additional data bytes following the first. The internal address is

automatically incremented and the next register is written. Once the internal address reaches its maximum value, it rolls

over to 0. The multiple write is concluded when the master sends another start or stop condition. In performing a multiple

write, the internal register address may be incremented or decremented (Section 5.2.2) for each write including the final.

FIGURE 5-4:

I2C SLAVE READS

Multiple Register Reads

Control Byte

Single Register Read

R/~W

Data Byte

Control Byte

Address Byte 1

Address Byte 0

13 12 11 10

Data Byte 1

Control Byte

Address Byte 1

Address Byte 0

13 12 11 10

R/~W

. D

Data Bytes

2 — (n-1)

Data Byte n

. D

DIR

Inc /

Dec /

Static

DIR

Inc /

Dec /

Static

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