UPD360 datasheet(75/221 Pages) MICROCHIP

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DS00002084C-page 75

UPD360

9.3.2

SINK DETACH DETECTION

The DFP detach is detected by the removal of VBUS. The VBUS comparator must always be enabled for the UFP to

detect this condition.

Software programs the VBUS Comparator Control to 00b and disables the VBUS debouncer.

Software polls VBUS_DB_ACTIVE until it reads back 0b to indicate that the VBUS debouncer is inactive.

Software programs the VBUS Debounce Register (VBUS_DEB) as required.

Software programs the CCx Sample Enable Registers (CCx_SAMP_EN) as required to enable the respective

threshold(s) debouncing.

Software enables VBUS_INT, which is then used to detect VBUS, via the VBUS Match Enable Register (VBUS_-

MATCH_EN).

Software enables IRQ_N by configuring the respective bit for VBUS_INT in the Interrupt Enable Register

(INT_EN).

Software enables the VBUS Comparator/DAC via the VBUS Comparator Control bit in the VBUS Control Regis-

ter (VBUS_CTL).

Software turns off all clock sources with the exception of 20 KHz keep-alive clock via the Clock Control Register

(CLK_CTL) to save power.

DFP removes VBUS.

10. After the VBUS debounce period, the VBUS Match Register (VBUS_MATCH) and VBUS Change Status Register

(VBUS_CHG_STS) are updated. The VBUS_INT interrupt asserts which in turn asserts IRQ_N.

11. Software continues to monitor VBUS to determine if it stays below vSafe5V for a duration of tPdDebounce.

9.4

DRP Operation

This section describes a usage of the device for implementing a DRP attach. In this configuration, software utilizes the

device to alternate between a Source and Sink advertisement with an interval of tDRP per the USB Type-C Specifica-

tion.

The steps for initially configuring the device to advertise Source capabilities follows the steps defined in Section 9.2.2,

"Source Attach Detection". Software must also implement the tDRP timer. If a Sink is not detected within this time, soft-

ware shall change the device’s role to Sink and again attempt an attach detection.

Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator.

Software programs the CC Comparator Control to 00b and disables the CC debouncer.

Software polls CC_DB_ACTIVE until it reads back to indicate the CC debouncer is inactive.

Software programs the Match Debounce Register (MATCH_DEB) as required for the tPDDebounce period.

Software programs the CC Threshold x Registers (CC_THRx) if required.

Software programs the CCx Debounce Clear Enable Registers (CCx_DBCLR_EN) and CCx Match Enable Reg-

isters (CCx_MATCH_EN) as required to match the thresholds of interest.

Software enables the CC_MATCH_VLD, CC1_MATCH_CHG and CC2_MATCH_CHG interrupts via the CC

Interrupt Enable Register (CC_INT_EN).

Software enables IRQ_N assertion by enabling the CC_INT in the Interrupt Enable Register (INT_EN).

Software programs the RP current sources via the CC1 RP Value and CC2 RP Value in the CC Control Register

(CC_CTL).

10. Software programs the CC Comparator Control to sample both CC pins and enable the CC debouncer. The

CC_DB_ACTIVE bit will assert soon after.

11. Software sets the Clock Control Register (CLK_CTL) to disable all clock sources accept for the keep alive clock.

If after time tDRP an attachment is not detected, software shall configure the device to be a Sink and attempt to detect

the presence of a Source. This is similar to the steps defined in Section 9.3.1, "Sink Attach Detection".

Software accesses the device via I2C/SPI which wakes the device up and enables the 48 MHz oscillator

Software programs the CC Comparator Control to 00b and disables the CC debouncer.

Note:

VBUS_THR0 and VBUS_THR1 are adjusted via the VBUS Threshold x Registers (VBUS_THRx) to

vSafe5V, if required.

Note:

Assertion of CC_MATCH_VLD indicates that the initial CC debounce of both CC pins has completed and

a valid value is available in the CCx Match Registers (CCx_MATCH).

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