AD7715_15 datasheet(27/40 Pages) AD

27 / 40 page

AD7715

Rev. D | Page 27 of 40

Because the FSYNC bit resets the digital filter, the full settling

time of 3 × 1/output rate must elapse before there is a new word

loaded to the output register on the part. If the DRDY signal is

low when FSYNC goes to a 0, the DRDY signal will not be reset

high by the FSYNC command. This is because the AD7715

recognizes that there is a word in the data register that has not

been read. The DRDY line stays low until an update of the data

before returning low again. A read from the data register resets

the DRDY signal high, and it does not return low until the

settling time of the filter has elapsed (from the FSYNC command)

and there is a valid new word in the data register. If the DRDY

line is high when the FSYNC command is issued, the DRDY

line will not return low until the settling time of the filter has

elapsed.

RESET INPUT

The RESET input on the AD7715 resets all the logic, the digital

filter, and the analog modulator while all on-chip registers are

reset to their default state. DRDY is driven high and the AD7715

ignores all communications to any of its registers while the

RESET input is low. When the RESET input returns high, the

AD7715 starts to process data, and DRDY returns low in 3 ×

1/output rate indicating a valid new word in the data register.

However, the AD7715 operates with its default setup conditions

after a reset and it is generally necessary to set up all registers

and carry out a calibration after a reset command.

The on-chip oscillator circuit of the AD7715 continues to func-

tion even when the RESET input is low. The master clock signal

continues to be available on the MCLK OUT pin. Therefore, in

applications where the system clock is provided by the clock of the

AD7715, the AD7715 produces an uninterrupted master clock

during RESET commands.

STANDBY MODE

The STBY bit in the communications register of the AD7715

allows the user to place the part in a power-down mode when it

is not required to provide conversion results. The AD7715 retains

the contents of all its on-chip registers (including the data register)

while in standby mode. When released from standby mode, the

part starts to process data and a new word is available in the

data register in 3 × 1/output rate from when a 0 is written to

the STBY bit.

The STBY bit does not affect the digital interface, and it does

not affect the status of the DRDY line. If DRDY is high when the

STBY bit is brought low, it will remain high until there is a valid

new word in the data register. If DRDY is low when the STBY

bit is brought low, it will remain low until the data register is

updated at which time the DRDY line returns high for 500 ×

tCLK IN before returning low again. If DRDY is low when the part

enters its standby mode (indicating a valid unread word in the

data register), the data register can be read while the part is in

standby. At the end of this read operation, the DRDY line will

be reset high as normal.

Placing the part in standby mode reduces the total current to

5 μA typical when the part is operated from an external master

clock provided this master clock is stopped. If the external clock

continues to run in standby mode, the standby current increases to

150 μA typical with 5 V supplies and 75 μA typical with 3.3 V

supplies. If a crystal or ceramic resonator is used as the clock

source, then the total current in standby mode is 400 μA typical

with 5 V supplies and 90 μA with 3.3 V supplies. This is because

the on-chip oscillator circuit continues to run when the part is

in its standby mode. This is important in applications where the

system clock is provided by the clock of the AD7715, so that the

AD7715 produces an uninterrupted master clock even when it

is in its standby mode.

ACCURACY

Σ-Δ ADCs, like VFCs and other integrating ADCs, do not

contain any source of nonmonotonicity and inherently offer

no missing codes performance. The AD7715 achieves excellent

linearity by the use of high quality, on-chip capacitors, which

have a very low capacitance/voltage coefficient. The device also

achieves low input drift through the use of chopper-stabilized

techniques in its input stage. To ensure excellent performance

over time and temperature, the AD7715 uses digital calibration

techniques which minimize offset and gain error.

DRIFT CONSIDERATIONS

The AD7715 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and dc

leakage currents at the sampling node are the primary sources

of offset voltage drift in the converter. The dc input leakage

current is essentially independent of the selected gain. Gain

drift within the converter depends primarily upon the temperature

tracking of the internal capacitors. It is not affected by leakage

currents.

Measurement errors due to offset drift or gain drift can be

eliminated at any time by recalibrating the converter. Using

the system calibration mode can also minimize offset and

gain errors in the signal conditioning circuitry. Integral and

differential linearity errors are not significantly affected by

temperature changes.

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