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AD9911/PCB Datasheet(PDF) 27 Page - Analog Devices

No. de pieza AD9911/PCB
Descripción Electrónicos  500 MSPS Direct Digital Synthesizer with 10-Bit DAC
PDF  44 Pages
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Fabricante Electrónico  AD [Analog Devices]
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AD9911/PCB Datasheet(HTML) 27 Page - Analog Devices

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AD9911
Rev. 0 | Page 27 of 44
SYNC_CLK
SYNC
CLOCK
DDS CORE
AMPLITUDE
MULTIPLIER ENABLE
ACR <12>
0
0
1
0
1
01
HOLD
INC/DEC EN
OUT
COS(X)
UP/DN
DATA
LOAD
EN
LINEAR SWEEP
ACCUMULATOR
PROFILE/SDIO_1:3
PINS
8
8-BIT BINARY
DOWN
COUNTER
10-BIT BINARY
UP/DOWN
COUNTER
INCREMENT/
DECREMENT
STEP SIZE
ACR <15:14>
TEST TONE
MODULATION
MUX
10
10
10
10
10
10
10
10
AMPLITUDE SCALE
FACTOR
REGISTER
(ACR) <0:9>
DAC
2
PROFILE REGISTERS
FOR
ASK MODULATION
MANUAL
RAMP UP/DOWN
(RU/RD)
AUTO RAMP
UP/DOWN
(RU/RD)
RAMP UP/DOWN
(RU/RD)
ENABLE
ACR <11>
LOAD ARR
TIMER
BIT ACR <10>
AMPLITUDE
RAMP RATE
REGISTER
(ACR BITS <23:16>)
Figure 46. Output Amplitude Control Configurations
Ramp Rate Timer
The ramp rate timer is a loadable 8-bit down counter. It
generates the clock signal to the 10-bit counter, which in turn
generates the internal scale factor. The formula for calculating
the amplitude ramp rate time is
( )
)
(
_
/
Hz
CLK
SYNC
x
t =
Δ
Where x is the decimal value in Register 00x06 Bits <23:16>.
At 500 MSPS operation (SYNC_CLK =125 MHz), the
minimum time interval between steps is 1/125 MHz × 1 = 8 ns.
The maximum time interval is (1/125 MHz) × 255 = 2.04 μs.
The ramp rate timer is loaded with the value of the ASF every
time the counter reaches 1 (decimal). This load and count down
operation continues for as long as the timer is enabled unless
the timer is forced to load before reaching a count of 1.
If the load ARR timer bit ACR <10> is set, the ramp rate timer
is loaded if any of the following three incidents transpire: an I/O
update occurs, a profile pin changes, or the timer reaches a
See through Table 13 through Table 18 for RU/RD pin
assignments.



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