AD9911

Rev. 0 | Page 35 of 44

REGISTER MAPS

CONTROL REGISTER MAP

Table 24.

Register

Name

(Address)

Bit

Range

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

Channel

Select

Register

(CSR)

(0x00)

<7:0>

Auxiliary

Channel 3

(W/R enable1)

Auxiliary

Channel 2

(W/R enable1)

Primary Channel 1

(W/R enable1)

Auxiliary

Channel 0

(W/R enable1)

Must

be 0

I/0 mode select <2:1>

LSB first

0xF0

Function

Register 1

(FR1)

(0x01)

<7:0>

Reference clock

input power

down

External power

down mode

Sync clock

disable

DAC reference

power down

Open

Test-

tone

enable

Manual

hardware

synchronization

Manual software

synchronization

0x00

<15:8>

Open

Profile pin configuration <14:12>

Ramp up/ramp

down <11:10>

Modulation Level <9:8>

0x00

<23:16>

VCO gain control

PLL divider ratio <22:18>

Charge pump control <17:16>

0x00

Function

Register 2

(FR2)

(0x02)

<7:0>

Multidevice

synchronization

slave enable

Multidevice

synchronization

master enable

Multidevice

synchronization

status

Multidevice

synchronization

mask

Open <3:2>

System clock offset <1:0>

0x00

<15:8>

All channels auto

clear sweep

accumulator

All channels

clear sweep

accumulator

All channels auto

clear phase

accumulator

All channels

clear phase

accumulator

Open <11:10>

Open <9:8>

0x00

I/O update to become active. The channel enable bits determine if the channel registers and/or profile registers are written to or not.