AD9911SLASHPCB datasheet(21/44 Pages) AD

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AD9911

Rev. 0 | Page 21 of 44

Table 4.

CLK_MODE_SEL Pin 24

FR1 <22:18> PLL, Bits = M

Oscillator Enabled

System Clock

(fSYSCLK)

Min/Max Frequency

Range (MHz)

High = 1.8 V Logic

4 ≤ M ≤ 20

Yes

fSYSCLK = fOSC × M

100 < fSYSCLK < 500

High = 1.8 V Logic

M < 4 or M > 20

Yes

fSYSCLK = fOSC

20 < fSYSCLK < 30

Low

4 ≤ M ≤ 20

fSYSCLK = fREF CLK × M

100 < fSYSCLK < 500

Low

M < 4 or M > 20

fSYSCLK = fREF CLK

0 < fSYSCLK < 500

Reference Clock Input Circuitry

The reference clock input circuitry has two modes of operation.

The first mode (logic low) configures the circuitry as an input

buffer. In this mode, the reference clock must be ac-coupled to

the input due to internal dc biasing. This mode supports either

differential or single-ended configurations. If single-ended

mode is desired, the complementary reference clock input

(Pin 23) should be decoupled to AVDD or AGND via a 0.1 μF

capacitor. The following three figures exemplify common

reference clock configurations for the AD9911.

1:1

BALUN

REF_CLK

PIN 23

REFERENCE

CLOCK

SOURCE

REF_CLK

PIN 22

25Ω

0.1µF

25Ω

Figure 38. Typical Reference Clock Configuration for Sine Wave Source

The reference clock inputs can also support an LVPECL or

PECL driver as the reference clock source.

REF_CLK

PIN 23

REF_CLK

PIN 22

0.1µF

LVPECL/

PECL

DRIVER

TERMINATION

Figure 39. Typical Reference Clock Configuration for LVPECL/PECL Source

For external crystal operation, both clock inputs must be dc-

coupled via the crystal leads and bypassed. Figure 40 shows the

configuration when a crystal is used.

REF_CLK

PIN 23

25MHz

XTAL

REF_CLK

PIN 22

39pF

Figure 40. Crystal Configuration for Reference Clock Source

SCALABLE DAC REFERENCE CURRENT CONTROL

MODE

Set the full-scale output current using bits CFR <9:8>, as shown

in Table 5.

Table 5.

CFR <9:8>

LSB Current State

Full-scale

Half-scale

Quarter-scale

Eighth-scale

POWER-DOWN FUNCTIONS

The AD9911 supports pin-controlled power-down plus numer-

ous software selectable power-down modes. Software controlled

power-down allows the input clock circuitry, DAC, and the

digital logic (for the primary and auxiliary DDS cores) to be

individually powered.

When the PWR_DWN_CTL input pin is high, the AD9911

enters power-down mode based on the FR1 <6> bit. When the

PWR_DWN_CTL input pin is low, the individual power-down

bits (CFR <7:4>) control the power-down modes of operation.

See the Control Register Descriptions section for further details.

SHIFT KEYING MODULATION

The AD9911 can perform 2-/4-/8- or 16-level modulation of

frequency, phase, or amplitude (FSK, PSK, ASK) by applying

data to the profile pins. SYNC_CLK must be enabled when

performing FSK, PSK, or ASK, while the auxiliary DDS cores

must be disabled. Digital power down (CSR Bit <7>) of the

auxiliary channels is recommended.

In addition, the AD9911 has the ability to ramp up or ramp

down the output amplitude before, during, or after a

modulation (FSK, PSK only) sequence. This is accomplished by

using the 10-bit output scalar. Profile pins or SDIO_1:3 pins can

be configured to initiate the ramp up/ramp down (RU/RD)

operation. See the Output Amplitude Control section for

further details.

In modulation mode, a set of control bits (CFR<23:22>)

determines the type (frequency, phase, or amplitude) of

modulation. The primary channel (CH1) has 16 profile

registers. Register Address 0x0A through Register Address 0x18

are profile registers for modulation of frequency, phase, or

amplitude. Register 0x04, Register 0x05, and Register 0x06 are

dedicated registers for frequency, phase, and amplitude,

respectively.

These registers contain the initial frequency, phase offset and

amplitude word. Frequency modulation is 32-bit resolution,

phase modulation is 14 bit, and amplitude is 10 bit. When

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