AD9911SLASHPCB datasheet(7/44 Pages) AD

7 / 44 page

AD9911

Rev. 0 | Page 7 of 44

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

I/O PORT TIMING CHARACTERISTICS

Maximum Frequency Clock (SCLK)

200

MHz

Minimum SCLK Pulse Width Low (tPWL)

1.6

Minimum SCLK Pulse Width High (tPWH)

2.2

Minimum Data Set-Up Time (tDS)

2.2

Minimum Data Hold Time

Minimum CSB Set-Up Time (tPRE)

1.0

Minimum Data Valid Time for Read Operation

MISCELLANEOUS TIMING CHARACTERISTICS

Master_Reset Minimum Pulse Width

Minimum pulse width = 1 sync clock period

I/O_Update Minimum Pulse Width

Minimum pulse width = 1 sync clock period

Minimum Set-Up Time (I/O_Update to

SYNC_CLK)

4.8

Rising edge to rising edge

Minimum Hold Time (I/O_Update to

SYNC_CLK)

Rising edge to rising edge

Minimum Set-Up Time (Profile Inputs to

SYNC_CLK)

5.4

Minimum Hold Time (Profile Inputs to

SYNC_CLK)

Minimum Set-Up Time (SDIO Inputs to

SYNC_CLK)

2.5

Minimum Hold Time (SDIO Inputs to

SYNC_CLK)

Propagation Delay Between REF_CLK and

SYNC_CLK

2.25

3.5

5.5

CMOS LOGIC INPUT

VIH

2.0

VIL

0.8

Logic 1 Current

μA

Logic 0 Current

−12

μA

Input Capacitance

CMOS LOGIC OUTPUTS (1 mA Load)

VOH

2.7

VOL

0.4

POWER SUPPLY

Total Power Dissipation—Single-Tone Mode

241

Dominated by supply variation

Total Power Dissipation—With Sweep

Accumulator

241

Dominated by supply variation

Total Power Dissipation—3 Spur

Reduction/Multitone Channels Active

351

Dominated by supply variation

Total Power Dissipation—Test-Tone

Modulation

264

Dominated by supply variation

Total Power Dissipation—Full Power Down

1.8

IAVDD—Single-Tone Mode

IAVDD— Sweep Accumulator, REF_CLK

Multiplier, and 10-Bit Output Scalar Enabled

IDVDD—Single-Tone Mode

IDVDD—Sweep Accumulator, REF_CLK

Multiplier, and 10-Bit Output Scalar Enabled

IDVDD_I/O

IDVDD = read

IDVDD_I/O

IDVDD = write

IAVDD Power-Down Mode

0.7

IDVDD Power-Down Mode

1.1

AD9911/PCB Datasheet(PDF) 7 Page - Analog Devices

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