AD9911

Rev. 0 | Page 29 of 44

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK

RELATIONSHIPS

I/O_UPDATE and SYNC_CLK are used together to transfer

data from the I/O buffer to the active registers in the device.

Data in the I/O buffer is inactive.

SYNC_CLK is a rising edge active signal. It is derived from

the system clock and a divide-by frequency divider of 4. The

SYNC_CLK is provided externally to synchronize external

hardware to the AD9911 internal clocks.

I/O_UPDATE initiates the start of a buffer transfer. It can be

sent synchronously or asynchronously relative to the

SYNC_CLK.

If the set-up time between these signals is met, then constant

latency (pipeline) to the DAC output exists. For example, if

repetitive changes to phase offset via the SPI port is desired, the

latency of those changes to the DAC output is constant,

otherwise a time uncertainty of one SYNC_CLK period will be

present.

The I/O UPDATE is sampled on the rising edge of the

SYNC_CLK. Therefore, I/O_UPDATE must have a minimum

pulse width greater than one SYNC_CLK period.

The timing diagram shown in Figure 47 depicts when data in

the I/O buffer is transferred to the active registers.

The I/O UPDATE is set up and held around the rising edge of

SYNC_CLK and has zero hold time and 4.8 ns setup time.

SYNC_CLK

SYSCLK

AB

NN

N – 1

DATA IN

REGISTERS

DATA IN

I/O BUFFERS

N

N + 1

N + 2

+ 1

I/O UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.

Figure 47. I/O_UPDATE Timing