AD9911SLASHPCB datasheet(24/44 Pages) AD

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AD9911

Rev. 0 | Page 24 of 44

MUX

PHASE SWEEP EN

PHASE

ACCUMULATOR

PHASE OFFSET

ADDER

CPW0

MUX

FREQ SWEEP EN

CTW0

AMP SWEEP EN

ACR

Z–1

COS(X)

RU/RD LOGIC

SWEEP FUNCTION LOGIC

DAC

MUX

Figure 41. Linear Sweep Capability

Setting the Rate of the Linear Sweep

The rate of the linear sweep is set by the intermediate step size

(delta-tuning word) between S0 and E0 (see Figure 42) and the

time spent (sweep ramp rate word) at each step. The resolution

of the delta-tuning word is 32 bits for frequency, 14 bits for

phase, and 10 bits for amplitude. The resolution for the delta

ramp rate word is 8 bits.

In linear sweep, the user programs a rising delta word (RDW,

E0. The falling delta word (FDW, Register 0x09) and falling

sweep ramp rate (FSRR, Register 0x07) apply when sweeping

from E0 to S0.

When programming, note that attention is required to prevent

overflow of the sweep. If the sweep accumulator is allowed to

overflow, an uncontrolled, continuous sweep operation occurs.

To avoid this, the magnitude of the rising or falling delta word

should be smaller than the difference between full scale and the

E0 value (full scale − E0). For a frequency sweep, full scale is

231−1. For a phase sweep, full scale is 214 −1. For an amplitude

sweep, full scale is 210−1.

The graph in Figure 42 displays a linear sweep up and then

down using a profile pin. Note that the no dwell bit is cleared. If

the no dwell bit (CFR<15>) is set, the sweep accumulator

returns to 0 upon reaching E0. For more information, see the

Linear Sweep No Dwell Mode section.

RDW

RSRR

FSRR

Δf,p,a

FDW

TIME

PROFILE PIN

Δf,p,a

Δt

Figure 42. Linear Sweep Mode

For a piecemeal or a nonlinear transition between S0 and E0,

the delta tuning words and ramp rate words can be repro-

grammed during the transition.

The formulae for calculating the step size of RDW or FDW are

CLK

SYNC

RDW

⎟

⎠

⎞

⎜

⎝

⎛

(Hz)

⎟

⎠

⎞

⎜

⎝

⎛

360

RDW

ΔΦ

⎟

⎠

⎞

⎜

⎝

⎛

RDW

DAC full-scale current

The formula for calculating delta time from RSRR or FSRR is

(

)

(

CLK

SYNC

RSRR

t =

At 500 MSPS operation (SYNC_CLK =125 MHz), the

minimum time interval between steps is 1/125 MHz × 1 = 8 ns.

The maximum time interval is (1/125 MHz) × 255 = 2.04 μs.

Frequency Linear Sweep Example

This section provides an example of a frequency linear sweep

followed by a description.

AFP CFR<23:22> =10, modulation level FR1<9:8> = 00, sweep

enable CFR<14> = 1, linear sweep no-dwell CFR<15> = 0.

In linear sweep mode, when the profile pin transitions from low

to high, the RDW is applied to the input of the sweep accumu-

lator and the RSRR register is loaded into the sweep rate timer.

The RDW accumulates at the rate given by the ramp rate

(RSRR) until the output equals the CTW1 register value. The

sweep is then complete and the output held constant in

frequency.

When the profile pin transitions from high to low, the FDW is

applied to the input of the sweep accumulator and the FSRR

The FDW accumulates at the rate given by the ramp rate

(FSRR) until the output equals the CTW0 register value. The

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