AD9911SLASHPCB datasheet(18/44 Pages) AD

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AD9911

Rev. 0 | Page 18 of 44

THEORY OF OPERATION

PRIMARY DDS CORE

The AD9911 has one complete DDS (Channel 1) that consists

of a 32-bit phase accumulator, a phase-to-amplitude converter,

and 10-bit DAC. Together, these digital blocks generate a sine

wave when the phase accumulator is clocked and the phase

increment value (frequency tuning word) is greater than 0. The

phase-to-amplitude converter translates phase information to

amplitude information by a cos (θ) operation.

The output frequency (fO) of the DDS is a function of the

rollover rate of the phase accumulator. The exact relationship is

shown in the following equation:

)

)(

(

≤

FTW

with

FTW

where:

fS = the system clock rate.

FTW = the frequency tuning word.

232 represents the capacity of the phase accumulator’.

The DDS core architecture also supports the capability to phase

offset the output signal. This is performed by the channel phase

offset word (CPOW). The CPOW is a 14-bit register that stores

a phase offset value. This value is added to the output of the

phase accumulator to offset the current phase of the output

signal. The exact value of phase offset is given by the following

equation:

⎟

⎠

⎞

⎜

⎝

⎛

360

CPOW

SPURKILLER/MULTITONE MODE AND TEST-TONE

MODULATION

The AD9911 is equipped with three auxiliary DDS cores

(Channel 0, Channel 2, and Channel 3). Because these channels

do not have a DAC, there is no direct output. Instead, these

channels are designed to implement either spur reduction/

multiple tones or test-tone modulation on the output spectrum

for Channel 1.

When using multitone mode, the device can output up to four

distinct carriers concurrently. This is possible via the summing

node for all four DDS cores. The frequency, phase and

amplitude of each tone is adjustable. The maximum amplitude

of the auxiliary channels is −12 db below the primary channel’s

maximum amplitude to prevent overdriving the DAC input.

The primary channel’s amplitude can be adjusted down to

achieve equal amplitude for all carriers.

When using SpurKiller mode, up to three spurs in the output

spectrum for Channel 1 are reducible (one per auxiliary

channel). To match an exact frequency using the three channels,

the spur must be harmonically related to the fundamental

frequency or the tuning word for Channel 1. A nonharmonic

spur may be impossible to match frequency.

Spur reduction is not as effective at lower fundamental

frequencies where SFDR performance is already very good. The

benefits of SpurKiller channels are virtually nonexistent when

the output frequency is less than 20% of the sampling

frequency.

Test-tone modulation is similar to amplitude modulation

options of a signal generator. For test-tone modulation,

auxiliary DDS Channel 0 is assigned to implement amplitude

sinusoidal modulated waveforms of the primary channel. This

function is programmed using internal registers.

D/A CONVERTER

The AD9911 incorporates a 10-bit current output DAC. The

DAC converts a digital code (amplitude) into a discrete analog

quantity. The DAC current outputs can be modeled as a current

source with high output impedance (typically 100 kΩ). Unlike

many DACs, these current outputs require termination into

AVDD via a resistor or a center-tapped transformer for

expected current flow.

The DAC has complementary outputs that provide a combined

full-scale output current (IOUT + IOUTB). The outputs always sink

current.

The full-scale current is controlled by means of an external

resistor (RSET) and the scalable DAC current control bits

discussed in the Modes of Operation section. The Resistor RSET

is connected between the DAC_RSET pin and analog ground

(AGND). The full-scale current is inversely proportional to the

resistor value as follows:

SET

OUT

Limiting the output to 10 mA with an RSET of 1.9 kΩ provides

optimal spurious-free dynamic range (SFDR) performance. The

DAC output voltage compliance range is AVDD + 0.5 V to

AVDD − 0.5 V. Voltages developed beyond this range can cause

excessive harmonic distortion. Proper attention should be paid

to the load termination to keep the output voltage within its

compliance range. Exceeding this range could damage the DAC

output circuitry.

DAC

IOUT

AVDD

1:1

50Ω

IOUT

LPF

Figure 35. Typical DAC Output Termination Configuration

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