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AD9911

Rev. 0 | Page 30 of 44

I/O PORT

OVERVIEW

The AD9911 I/O port offers multiple configurations to provide

significant flexibility. The I/O port includes an SPI-compatible

mode of operation. Flexibility is provided by four data

(SDIO_0:3) pins supporting four programmable modes of I/O

operation.

Three of the four data pins (SDIO_1:3) can be used for

functions other than I/O port operation. These pins may be set

to initiate a ramp-up or ramp-down (RU/RD) of the 10-bit

amplitude output scalar. One of these pins (SDIO_3) may be

used to provide the SYNC_I/O function.

The maximum speed of the I/O port SCLK is 200 MHz. The

maximum data throughput of 800 Mbps is achieved by using all

SDIO_0:3 pins.

There are four sets of addresses (0x03 to 0x18) that channel

enable bits can access to provide channel independence when

using the auxiliary DDS cores for either test-tone generation or

spur killing. See the Control Register Descriptions section for

further discussion of programming channels that are common

or independent from one another.

I/O operation of the AD9911 occurs at the register level, not the

byte level; the controller expects that all byte(s) contained in the

used to abort an I/O operation, thereby not allowing all bytes to

be accessed. This feature can be used to program only a part of

the addressed register. Note that only completed bytes are

stored.

There are two phases to a communications cycle. The first is the

instruction phase, which writes the instruction byte into the

AD9911. Each bit of the instruction byte is registered on each

corresponding rising edge of SCLK. The instruction byte

defines whether the upcoming data transfer is a write or read

operation and contains the serial address of the address register.

Phase 2 of the I/O cycle is of the data transfer (write/read)

between the I/O port controller and the I/O port buffer. The

number of bytes transferred during this phase of the communi-

cation cycle is a function of the register being accessed. The

actual number of additional SCLK rising edges required for the

data transfer and instruction byte depends on the number of

byte(s) in the register and the I/O mode of operation.

For example, when accessing Function Register 1, (FR1), which

is three bytes wide, Phase 2 of the I/O cycle requires that three

bytes are transferred. After transferring all data bytes per the

instruction byte, the communication cycle is complete.

Upon completion of a communication cycle, the AD9911 I/O

port controller expects the next set of rising SCLK edges to be

the instruction byte for the next communication cycle. Data

writes occur on the rising edge of SCLK. Data reads occur on

the falling edge of SCLK. See Figure 43 and Figure 44.

An I/O_UPDATE transfers data from the I/O port buffer to

active registers. The I/O_UPDATE can either be sent for each

communication cycle or when all I/O operations are complete.

Data remains inactive until an I/O_UPDATE is sent, with the

exception of the channel enable bits in the Channel Select

enabled.

tPRE

tDSU

tSCLK

tSCLKPWL

tSCLKPWH

tDHLD

SCLK

SDIO

SYMBOL

DEFINITION

tPRE

CS SETUP TIME

tSCLK

PERIOD OF SERIAL DATA CLOCK

tSCLKPWH

SERIAL DATA SETUP TIME

tSCLKPWL

SERIAL DATA CLOCK PULSE WIDTH HIGH

tDHLD

SERIAL DATA CLOCK PULSE WIDTH LOW

tDSU

SERIAL DATA HOLD TIME

MIN

1.0ns

2.2ns

5.0ns

2.2ns

1.6ns

0ns

Figure 48. Set-Up and Hold Timing for the I/O Port

tDV

SCLK

SDIO

SDO (SDIO_2)

SYMBOL

DEFINITION

MIN

DATA VALID TIME

12ns

Figure 49. Timing Diagram for Data Read for I/O Port

INSTRUCTION BYTE DESCRIPTION

The instruction byte contains the information displayed in

Table 22 where x = don’t care.

Table 22.

MSB

LSB

R/Wb

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