AD9911SLASHPCB datasheet(32/44 Pages) AD

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AD9911

Rev. 0 | Page 32 of 44

Single-Bit Serial (2- and 3-Wire) Modes

The single-bit serial mode interface allows read/write access to

all registers that configure the AD9911. MSB-first or LSB-first

transfer formats and the SYNC_I/O function are supported.

In 2-wire mode, the SDIO_0 pin is the single serial data I/O pin.

In 3-wire mode, the SDIO_0 pin is the serial data input pin and

the SDIO_2 pin is the output. For both modes, the SDIO_3 pin

is configured as an input and operates as the SYNC_I/O pin.

The SDIO_1 pin is unused.

2-Bit Mode

The SPI port operation in 2-bit mode is identical to the SPI port

operation in single bit mode, except that two bits of data are

registered on each rising edge of SCLK, cutting in half the

number of cycles required to program the device. The SDIO_0

pin contains the even numbered data bits using the notation D

<7:0> while the SDIO_1 pin contains the odd numbered data

bits regardless of whether in MSB- or LSB-first format (see

Figure 47).

4-Bit Mode

The SPI port in 4-bit mode is identical to the SPI port in single

bit mode, except that four bits of data are registered on each

rising edge of SCLK.

This reduces by 75% the number of cycles required to program

the device. Note that when reprogramming the device for 4-bit

mode, it is important to keep the SDIO_3 pin at Logic 0 until

the device is programmed out of the single bit serial mode.

Failure to do so can result in the I/O port controller being out of

sequence.

Figure 50 through Figure 52 are write timing diagrams for the

I/O modes available. Both MSB and LSB-first modes are shown.

LSB-first bits are shown in parenthesis. The clock stall low/high

feature shown is not required, but rather is used to show that

data (SDIO) must have the proper setup time relative to the

rising edge of SCLK.

Figure 53 through Figure 56 are read timing diagrams for each

I/O mode available. Both MSB and LSB-first modes are shown.

LSB-first bits are shown in parenthesis. The clock stall low/high

feature shown is not required. It is used to show that data

(SDIO) must have the proper set-up time relative to the rising

edge of SCLK for the instruction byte and the read data that

follows the falling edge of SCLK.

SCLK

SDIO_0

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

(I0)

(I1)

(I2)

(I3)

(I4)

(I5)

(I6)

(I7)

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

Figure 50. Single-Bit Serial Mode Write Timing—Clock Stall Low