PM0223 datasheet(21/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

The memory types are:

The different ordering requirements for Device and Strongly-ordered memory mean that the

memory system can buffer a write to Device memory, but must not buffer a write to Strongly-

ordered memory.

The additional memory attributes include.

2.2.2

Memory system ordering of memory accesses

For most memory accesses caused by explicit memory access instructions, the memory

system does not guarantee that the order in which the accesses complete matches the pro-

gram order of the instructions, providing any re-ordering does not affect the behavior of the

instruction sequence. Normally, if correct program execution depends on two memory

accesses completing in program order, software must insert a memory barrier instruction

between the memory access instructions, see 2.2.2: Memory system ordering of memory

accesses on page 21.

However, the memory system does guarantee some ordering of accesses to Device and

Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs

before A2 in program order, the ordering of the memory accesses caused by two instruc-

tions is:

Normal

The processor can re-order transactions for efficiency, or

perform speculative reads.

Device

The processor preserves transaction order relative to other

transactions to Device or Strongly-ordered memory.

Strongly-ordered

The processor preserves transaction order relative to all other

transactions.

Shareable

For a shareable memory region, the memory system provides

data synchronization between bus masters in a system with

multiple bus masters, for example, a processor with a DMA

controller.

Strongly-ordered memory is always shareable.

If multiple bus masters can access a non-shareable memory

region, software must ensure data coherency between the

bus masters.

<This description is required only if the device is likely to be

used in systems where memory is shared between multiple

processors.>

Execute Never (XN)

Means the processor prevents instruction accesses. A

HardFault exception is generated on executing an instruction

fetched from an XN region of memory.

PM0223 Datasheet(PDF) 21 Page - STMicroelectronics

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