PM0223 datasheet(94/110 Pages) STMICROELECTRONICS

94 / 110 page

STM32L0 Core Peripherals

PM0223

94/110

DocID025763 Rev 1

4.3.8

System Handler Priority Registers

The SHPR2-SHPR3 registers set the priority level, 0 to 192, of the system exception

handlers that have configurable priority.

SHPR2-SHPR3 are word accessible. See the register summary in for their attributes.

To access the system exception priority level using CMSIS, use the following CMSIS

functions:

•

uint32_t NVIC_GetPriority(IRQn_Type IRQn)

•

void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)

The input parameter IRQn is the IRQ number, see Table 13 on page 27 for more

information.

The system handlers, and the priority field and register for each handler are:

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:6] of each field,

and bits[5:0] read as zero and ignore writes.

System Handler Priority Register 2

The bit assignments are:

Bits 8:4

Reserved, must be kept cleared

Bit 3

UNALIGN_ TRP

Always reads as one, indicates that all unaligned accesses generate a HardFault.

Bit 2:0

Reserved, must be kept cleared

Table 32. System fault handler priority fields

Handler

Field

SVCall

PRI_11

System Handler Priority Register 2 on page 94.

PendSV

PRI_14

System Handler Priority Register 3 on page 95.

SysTick

PRI_15

Reserved

PRI_6[7:4]

PRI_6[3:0]

5432

PRI_5[7:4]

PRI_5[3:0]

PRI_4[7:4]

Bits 31:24

PRI_11: Priority of system handler 11, SVCall.

Bits 23:0

Reserved, must be kept cleared

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