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PM0223 Datasheet(PDF) 100 Page - STMicroelectronics |
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PM0223 Datasheet(HTML) 100 Page - STMicroelectronics |
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100 / 110 page ![]() STM32L0 Core Peripherals PM0223 100/110 DocID025763 Rev 1 4.5.2 MPU Control Register The MPU_CTRL register: • Enables the MPU. • Enables the default memory map background region. • Enables use of the MPU when in the HardFault or Non-Maskable Interrupt (NMI) handler. See the register summary in Table 35 on page 99 for the MPU_CTRL attributes. The bit assignments are: 15 14 13 12 11 10 9 8 76 5432 1 0 DREGION[7:0] Reserved SEPA RATE r rrrr r r r r Bits 31:24 Reserved. Bits 23:16 IREGION[7:0]: Indicates the number of supported MPU instruction regions. Always contains 0x00. The MPU memory map is unified and is described by the DREGION field. Bits 15:8 DREGION[7:0]: Indicates the number of supported MPU data regions: 0x00 = Zero regions if your device does not include the MPU. 0x08 = Eight regions if your device includes the MPU. Bits 7:1 Reserved. Bit 0 SEPARATE: Indicates support for unified or separate instruction and date memory maps: 0 = Unified. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 76 5432 1 0 Reserved PRIVD EFENA HFNMI ENA EN ABLE rw rw rw |
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