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PM0223 Datasheet(PDF) 15 Page - STMicroelectronics |
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PM0223 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 110 page ![]() DocID025763 Rev 1 15/110 PM0223 The STM32L0 Cortex-M0+ Processor 35 Figure 3. APSR, IPSR and EPSR bit assignments Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • Read all of the registers using PSR with the MRS instruction. • Write to the APSR using APSR with the MSR instruction. The PSR combinations and attributes are: See the instruction descriptions MRS on page 74 and MSR on page 75 for more information about how to access the program status registers. Application Program Status Register The APSR contains the current state of the condition flags, from previous instruction execu- tions. See the register summary in Table 3 on page 13 for its attributes. The bit assignments are: Table 4. PSR register combinations Register Type Combination PSR RW(1),(2) 1. The processor ignores writes to the IPSR bits. 2. Reads of the EPSR bits return zero, and the processor ignores writes to these bits. APSR, EPSR, and IPSR. IEPSR RO EPSR and IPSR. IAPSR RW(1) APSR and IPSR. EAPSR RW(2) APSR and EPSR. Table 5. APSR bit assignment Bits Name Description [31] N Negative flag. [30] Z Zero flag. [29] C Carry or borrow flag. |
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