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PM0223 Datasheet(PDF) 57 Page - STMicroelectronics

No. de pieza PM0223
Descripción Electrónicos  This programming manual provides information for application and system-level software developers
PDF  110 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PM0223 Datasheet(HTML) 57 Page - STMicroelectronics

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PM0223
The STM32L0 Cortex-M0+ Instruction Set
80
3.5.3
ASR, LSL, LSR, and ROR
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.
Syntax
ASRS {Rd,} Rm, Rs
ASRS {Rd,} Rm, #imm
LSLS {Rd,} Rm, Rs
LSLS {Rd,} Rm, #imm
LSRS {Rd,} Rm, Rs
LSRS {Rd,} Rm, #imm
RORS {Rd,} Rm, Rs
where:
Note:
MOVS Rd
, Rm is a pseudonym for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR,
and ROR perform an arithmetic-shift-left, logical-shift-left, logical-shift-
right or a right-rotation of the bits in the register Rm by the number of places specified by the
immediate imm or the value in the least-significant byte of the register specified by Rs.
For details on what result is generated by the different instructions, see 3.3.3: Shift
Operations on page 40.
Restrictions
In these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate
instructions, Rd and Rm must specify the same register.
Condition flags
These instructions update the N and Z flags according to the result.
The C flag is updated to the last bit shifted out, except when the shift length is 0, see 3.3.3:
Shift Operations on page 40. The V flag is left unmodified.
Rd
Is the destination register. If Rd is omitted, it is assumed to take the same
value as Rm.
Rm
Is the register holding the value to be shifted.
Rs
Is the register holding the shift length to apply to the value in Rm
Imm
Is the shift length. The range of shift length depends on the instruction:
ASR
shift length from 1 to 32
LSL
shift length from 0 to 31
LSR
shift length from 1 to 32.



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