LAN8808D datasheet(16/80 Pages) MICROCHIP

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LAN8808D

DS00005833C-page 16

TABLE 3-5:

MISCELLANEOUS PINS

Name

Symbol

Buffer

Type

Description

Management

Interface Data

MDIO

VIS/

VO12

VOD12

PHY Management data interface.

Note:

An external pull-up resistor to VDDIO in the range of

1.0 kΩ to 4.7 kΩ is required (1.0 kΩ for high-speed

MDIO operation).

The buffer type (push-pull or open-drain/open-source)

depends on the setting of the MDIO Buffer Type bit in the Out-

put Control register, as well as the disable_mdo_drv bit in each

port’s direct register 17.

See Section 5.14.1, High-Speed MDIO Operation for addi-

tional details.

Management

Interface Clock

MDC

VIS

PHY Management clock input.

PHY Interrupt

INT_N

VO12/

VOD12

(PU)

Programmable interrupt output.

The buffer type (push-pull or open-drain) depends on the set-

ting of the INT Buffer Type bit in the Output Control register

and defaults to open-drain.

The polarity depends on the setting of the Intr Polarity Invert bit

in the Control register and defaults to active low.

Start of Frame

Ports 3-0

SOF[3:0]

SRL

RX and TX Start of Frame indicator. A pulse indicates Start of

Frame is detected on the selected transmit or receive port.

These pins can be configured via the GPIO SOF Select regis-

ter. This pin is shared with other functions.

General Purpose

I/O

GPIO23

GPIO[21:1]

VIS/VO12/

VOD12/

SRL

(PU)

General purpose I/O.

These I/Os are shared with various other functions. Buffer type

and alternate function selection is configured via GPIO regis-

ters.

Symbol

Buffer Type

Description

VIS/

VO12/

VOD12

(PU)

SRL

(PU)

GPIO[1:2]