LAN8808D datasheet(45/80 Pages) MICROCHIP

45 / 80 page

LAN8808D

DS00005833C-page 45

5.14.2

ALL PHYS ADDRESS

Normally, the Ethernet PHYs are accessed at the PHY addresses set by the PHYAD[4:0] strapping pins.

PHY Address 0h is optionally supported as the broadcast PHY address, which allows for a single write command to

simultaneously program an identical PHY register for two or more PHY devices (for example, using PHY Address 0h to

set the Basic Control register to a value of 0x1940 to set bit[11] to a value of one to enable software power-down).

PHY Address 0 is enabled (in addition to the PHY address set by the PHYAD[4:0] strapping pins) when the All-PHYAD

Enable bit in the Common Control register is set to ‘1’.

5.14.3

MDIO OUTPUT DRIVE MODE

The MDIO output pin drive mode is controlled by the MDIO Buffer Type bit in the Output Control register. When set to

a ‘0’, the MDIO output is open-drain. When set to ‘1’, the MDIO output is push-pull.

5.15

Interrupts

The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status

update in the device. The Interrupt Enable register contains the interrupt control bits that enable and disable the condi-

tions for asserting the INT_N signal. The Interrupt Status register contains the interrupt status bits that indicate which

interrupt conditions have occurred. Most interrupt status bits are cleared upon reading. Some bits are read only and

have a lower level register to indicate individual sources.

The interrupt structure of the device is detailed in Figure 5-8.

The INT_N buffer type is selectable between open-drain and push-pull and is configured by the INT Buffer Type field in

the Output Control register. The default is open-drain.

The Intr Polarity Invert bit in the Control register sets the interrupt level to active high or active low. The default is active

low. If the buffer type is set to open-drain, the polarity is forced to be active low.

Note:

Bits in the Interrupt Status register are set by the interrupt events regardless of the value of the correspond-

ing bits in the Interrupt Enable register.

FIGURE 5-8:

INTERRUPT STRUCTURE

INT_N

Chip-Level

Interrupt

Chip-Level

Interrupt Status Register

GPHY_Hard_Macro_x

Interrupt

Logical

GPHY Hard Macro x

GPHY

Interrupt

Enable

GPIOs

Interrupt

Logical

GPIO

Interrupt

Enable

AB PVT

Interrupt

Logical

AB PVT

Interrupt

Mask

Interrupt

Sources

GPHY ISR

Interrupt

Sources

GPIO ISR

Interrupt

Sources

AB PVT ISR

GPIOs

Temperature Monitor

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