LAN8808D datasheet(53/80 Pages) MICROCHIP

53 / 80 page

LAN8808D

DS00005833C-page 53

5.19

PLL/Clocks and Resets

The device provides the following PLLs:

• System PLL: Generates the internal system clocks and clocks required for the internal PHYs. See Section 5.19.1,

"System Clocks" for additional information.

• QSGMII SerDes MPLL: Generates the clocks needed by the SerDes. See Section 5.19.2, "QSGMII SerDes

Clock" for additional information.

The reference clock selection of the System PLL and QSGMII SerDes MPLL are controlled via the REF_CLK_SEL1

pins. Refer to Table 3-5 for detailed REF_CLK_SEL1 setting information.

5.19.1

SYSTEM CLOCKS

System clocks are generated by the System PLL and are used for many common (not port-specific) functions such as

QSGMII TX and configuration registers. These clocks are also selectable by each PHY port for use as PHY TX timing.

The System PLL generates the following clocks:

• 250 MHz system clock

• 25 MHz system clock

The System PLL can use any of the following as its input reference clock:

• 25 MHz system single-ended reference clock input (not recommended)

• 125 MHz system differential clock inputs (recommended for best QSGMII performance)

5.19.2

QSGMII SERDES CLOCK

The 250 MHz QSGMII SerDes clock is generated by the SerDes MPLL.

The QSGMII SerDes MPLL can use any of these as its input reference clock:

• 25 MHz system clock from single-ended external clock input (not recommended)

• 125 MHz system differential clock inputs (recommended for best QSGMII performance)

5.19.3

RESETS

The device supports the following software resets from configuration registers:

• Chip hard and soft resets (all logic and macros in the chip)

- Chip soft reset (EP4.9) does not reset the Gigabit PHYs. If needed, the GPHY Hard Macro soft reset must be

used for this.

- GPHY resistor calibration is also run based on the chip hard reset.

• QSGMII hard and soft resets (QSGMII SerDes, extender, and per-port PCS1Gs)

• QSGMII SerDes transmitter and receiver resets

• Port hard and soft resets (all port-specific logic and macros in each port)

- Neither port hard reset (EP5.80) nor soft reset (EP5.81) will reset the GPHY. If needed, the GPHY Macro hard

or soft reset must be used for this.

• Gigabit PHY hard macro hard and soft resets (per port)

The device also provides a RESET_N input pin. This pin must adhere to the timing requirements detailed in Section

6.6.2, "Power Sequence Timing" and Section 6.6.3, "Reset Pin Configuration Strap Timing". Release from reset is based

on the RESET_N input pin transitioning from low to high.

5.19.4

POWER ON READY (POR) WITH OVER/UNDER VOLTAGE PROTECTION

POR monitors three voltages (Refer to Table 6-10 for the exact specification):

• +1.21V Analog Power Supply (on VDDAL_x) set for ~0.8V (typical) - it is assumed that VDDCORE and VDDAL_x

are externally connected, therefore VDD is indirectly monitored.

• +2.5/3.3V Analog Power Supply (on VDDAH_x) set for ~2.1V (typical)

LAN8808D Datasheet(PDF) 53 Page - Microchip Technology

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