LAN8808D datasheet(4/80 Pages) MICROCHIP

4 / 80 page

LAN8808D

DS00005833C-page 4

MDI

Medium Dependent Interface

MDIO

Management Data Input/Output

MDIX

Media Dependent Interface with crossover

MII

Media Independent Interface

MLT-3

Multi-Level Transmission Encoding (3-levels). A tri-level encoding method where a

change in the logic level represents a code bit “1” and the logic output remaining at the

same level represents a code bit “0”

N/A

Not Applicable

No Connect

NLP

Normal Link Pulse

MMD

MDIO Manageable Device

MSE

Mean Squared Error

OCXO

Oven Controlled Crystal (Xtal) Oscillator

PAM5

5-level Pulse Amplitude Modulation

PCS

Physical Coding Sublayer

PEC

Packet-based Equipment Clock

PHY

Physical layer

PLL

Phase-Locked Loop

POR

Power On Ready

QSGMII

Quad Serial Gigabit Media Independent Interface

RESERVED

Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must

always be zero for write operations. Unless otherwise noted, values are not guaran-

teed when reading reserved bits. Unless otherwise noted, do not read or write to

reserved addresses.

SerDes

Serializer/Deserializer

SFD

Start of Frame Delimiter. The 8-bit value indicating the end of the preamble of an

Ethernet frame.

SMD

Start mPacket Delimiter

SNR

Signal to Noise Ratio

SoC

System-on-Chip

SOF

Start of Frame

SPD

Start of Packet Delimiter. Used in QSGMII

Software Power-Down

TABLE 1-1:

GENERAL TERMS (CONTINUED)

Term

Description

LAN8808D Datasheet(PDF) 4 Page - Microchip Technology

LAN8808D Datasheet(HTML) 4 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Descarga

Enlace URL