LAN8808D datasheet(36/80 Pages) MICROCHIP

36 / 80 page

LAN8808D

DS00005833C-page 36

5.8.2

RECEIVE DIRECTION CONTROL (PHY-TO-MAC)

The PHY enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/Refresh) from its

EEE-compliant Link Partner. The PHY will pass the Sleep Request to the attached EEE-compliant MAC. The PHY

remains in the receive LPI Sleep state while it continues to receive Refreshes from its Link Partner, and it will continue

to inform the attached EEE-compliant MAC that it is in the receive LPI Sleep state. When the PHY receives a non /P/

code bit pattern (non-refresh), it exits the receive LPI Sleep state and signals a normal frame or normal idle to the

attached EEE-compliant MAC.

5.9

IEEE 802.3-2018 Frame Preemption

IEEE Standard 802.3-2018 [1] specifies a method for interspersing express traffic by preempting the transmission of a

normal packet, transmitting the express packet and then resuming the normal packet. The receiver likewise reassem-

bles the fragmented normal packet.

The preemption and reassembly is performed using a newly defined mPacket format. This mPacket format starts with

the normal preamble but supplements the normal Start of Frame Delimiter (SFD = 0xD5) with newly defined Start

mPacket Delimiters (SMDs) of various values. Also added for certain mPackets is a fragment count octet.

If Frame Preemption is not in use, the SFD appears ahead of every Ethernet frame on the PHY port. If Frame Preemp-

tion is in use, one of several possible SMDs may appear in place of the SFD on the PHY ports. The SMD and SFD

characters are passed transparently across QSGMII.

Section 5.10, "Start of Frame Indication" defines SOF pulse generation support for the SMDs.

5.10

Start of Frame Indication

The device supports the generation of an SOF pulse for the receive and transmit paths. Four SOF outputs are available,

each of which is configurable to be any of the eight available SOF pulses (TX SOF and RX SOF on each port). The SOF

pulse is generated when the Start of Frame Delimiter (SFD octet 0xD5 immediately following the preamble) is detected

by the PCS and can be output onto any enabled GPIO pin by setting the corresponding bits in the General Purpose IO

Data Select 1 register (GPIO_DATA_SEL1) or the General Purpose IO Data Select 2 register (GPIO_DATA_SEL2). The

SOF pulse is always active high. For details on SOF detection timing, refer to Section 6.6.8, "GPIO SOF Detection Tim-

ing".

The SOF pulse can also be configured to detect 802.3-2018 SMDs. When the SOF_preemption_enable bits in MMD2

continuation frame: SMD-V (0x07), SMD-R (0x19), SMD-E (0xD5) and SMD-S[0,1,2,3] (0xE6, 0x4C, 0x7F or 0xB3).

When the SOF_preemption_enable bits are set to ‘11’, the SOF pulse is also generated for the continuation SMD val-

ues: SMD-C[0,1,2,3] (0x61, 0x52, 0x9E or 0x2A).

5.11

Signal Quality Index

5.11.1

BACKGROUND

MLT-3 modulation is used for data transmission in 100BASE-TX and PAM5 modulation is used for data transmission in

1000BASE-T.

Logically, 100BASE-TX (MLT-3) and 1000BASE-T (PAM5) have signal values of {-1, 0, +1} and {-2, -1, 0, +1, +2},

respectively. These logic levels are mapped to slicer reference levels of {-128, 0, 128} for 100BASE-TX and {-128, -64,

0, 64, 128} for 1000BASE-T. The middle points (the compare thresholds) are {-64, 64} for 100BASE-TX and are {-96, -

32, 32, 96} for 1000BASE-T.

APPLICATION NOTE: Preemption is not supported at 10 Mbps.

Note:

The GPIO needs to be enabled and its direction set as an output via the General Purpose IO Enable reg-

ister (GPIO_EN) and the General Purpose IO Direction register (GPIO_DIR). The GPIO Buffer Type (GPI-

O_BUF) field in the General Purpose IO Buffer Type register (GPIO_BUF) also applies.

LAN8808D Datasheet(PDF) 36 Page - Microchip Technology

LAN8808D Datasheet(HTML) 36 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Descarga

Enlace URL