LAN8808D datasheet(65/80 Pages) MICROCHIP

65 / 80 page

LAN8808D

DS00005833C-page 65

6.6.2

POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements.

There is no power sequence requirement between transceiver (VDDAH_x), 1.21V core (VDDCORE, VDDAL_x,

VDDAL_TXL_SERDES), and digital I/O (VDDIO, VDDIO_1) power rails.

The power-up waveforms must be monotonic for all supply voltages to the device.

RESET_N must be held asserted following stable voltages for the minimum period specified and if re-asserted, for the

minimum period specified.

Before the next power-up cycle, all supply voltages to the device must reach less than 0.4V and there must be a mini-

mum wait time of 150 ms from power-off to power-on.

FIGURE 6-2:

POWER SEQUENCE TIMING INTERNAL REGULATORS

TABLE 6-11:

POWER SEQUENCING TIMING VALUES

Symbol

Description

Min

Typ

Max

Unit

tvr

Supply voltages rise time (must be monotonic)

0.1

—

100

tsr

Stable supply voltages to de-assertion of reset

100

—

trstia

RESET_N input assertion time

—

µs

tscrd

Stable external clock references to de-assertion of reset

—

tpc

Supply voltages cycle off-to-on time

150

—

VDDAL_x,

VDDAL_TXL_SERDES,

VDDCORE

VDDAH_x,

VDDIO, VDDIO_1

tvr

RESET_N

trstia

External Clock Inputs

tscrd

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