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LAN8808D Datasheet(PDF) 15 Page - Microchip Technology |
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LAN8808D Datasheet(HTML) 15 Page - Microchip Technology |
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15 / 80 page ![]() LAN8808D © 2026 Microchip Technology Inc. and its subsidiaries DS00005833C-page 15 Ethernet Port 3 TX/RX Negative Channel C TX_RXN_C_3 AIO Port 3 Channel C negative signal of differential pair Ethernet Port 3 TX/RX Positive Channel D TX_RXP_D_3 AIO Port 3 Channel D positive signal of differential pair Ethernet Port 3 TX/RX Negative Channel D TX_RXN_D_3 AIO Port 3 Channel D negative signal of differential pair TABLE 3-3: QSGMII INTERFACE PINS Name Symbol Buffer Type Description QSGMII Transmit- ter Output Positive QSGMII_TXP AO QSGMII PHY to MAC positive signal of differential pair QSGMII Transmit- ter Output Nega- tive QSGMII_TXN AO QSGMII PHY to MAC negative signal of differential pair QSGMII Receiver Input Positive QSGMII_RXP AI QSGMII MAC to PHY positive signal of differential pair QSGMII Receiver Input Negative QSGMII_RXN AI QSGMII MAC to PHY negative signal of differential pair TABLE 3-4: SYSTEM CLOCK PINS Name Symbol Buffer Type Description System Reference Clock Input XI ICLK The System Reference Clock can be input from XI (25 MHz single-ended) or CK125_REF_INP/M (125 MHz differential) as determined by REF_CLK_SEL1. Refer to REF_CLK_SEL1 for additional information. 125 MHz differential clock reference is recommended for best QSGMII performance. System Reference Clock Input Positive CK125_REF_INP LVDS1 The System Reference Clock can be input from XI (25 MHz single-ended) or CK125_REF_INP/M (125 MHz differential) as determined by REF_CLK_SEL1. Refer to REF_CLK_SEL1 for additional information. 125 MHz differential clock reference is recommended for best QSGMII performance. System Reference Clock Input Negative CK125_REF_INM LVDS1 The System Reference Clock can be input from XI (25 MHz single-ended) or CK125_REF_INP/M (125 MHz differential) as determined by REF_CLK_SEL1. Refer to REF_CLK_SEL1 for additional information. 125 MHz differential clock reference is recommended for best QSGMII performance. TABLE 3-2: ETHERNET MEDIA INTERFACE PINS (CONTINUED) Name Symbol Buffer Type Description |
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