PC87311A datasheet(23/78 Pages) NSC

23 / 78 page

30 FDC Register Description (Continued)

Disk Changed

Active low status of DSKCHG disk

interface input During power down this bit will be

invalid if it is read by the software

D6 – D4 Reserved

Always 0

DMA Enable

Active high status of the DMAEN bit

in the DOR

No Precompensation

Active high status of the

NOPRE bit in the CCR

D1D0 Data Rate Select 10

These bits indicate the

status of the DRATE 10 bits programmed through

the DSRCCR

39 CONFIGURATION CONTROL REGISTER (CCR)

Write Only

This is the write-only data rate register commonly used in

PC-AT applications This register is not affected by a soft-

ware reset and is set to 250 kbs after a hardware reset

The data rate of the floppy controller is determined by the

last write to either the CCR or DSR

391 CCRPC-AT and PS2 Modes

DESC

000000

DRATE1

DRATE0

RESET

COND

D7–D2 Reserved

Should be set to 0

D1D0 Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-6 for

the appropriate values

392 CCRModel 30 Mode

DESC

NOPRE

DRATE1

DRATE0

RESET

COND

D7–D3 Reserved

Should be set to 0

No Precompensation

This bit can be set by soft-

ware but it has no functionality It can be read by bit

D2 of the DIR when in the Model 30 register mode

Unaffected by a software reset

D1D0 Data Rate Select 10

These bits determine the

data rate of the floppy controller See Table 3-6 for

the appropriate values

310 RESULT PHASE STATUS REGISTERS

The Result Phase of a command contains bytes that hold

status information The format of these bytes is described

below Do not confuse these status bytes with the Main

Status Register which is a read only register that is always

valid The Result Phase status registers are read from the

Data Register (FIFO) only during the Result Phase of certain

commands (see Section 41 Command Set Summary) The

status of each register bit is indicated when the bit is a 1

3101 Status Register 0 (ST0)

DESC

HDS

DS1

DS0

RESET

COND

D7–D6 Interrupt Code

00 e Normal Termination of Command

01 e Abnormal Termination of Command Execu-

tion of command was started but was not

successfully completed

10 e Invalid Command Issued Command issued

was not recognized as a valid command

11 e Internal drive ready status changed state dur-

ing the drive polling mode Only occurs after a

hardware or software reset

Seek End

Seek Relative Seek or Recalibrate

command completed by the controller (Used during

a Sense Interrupt command)

Equipment Check

After a Recalibrate command

Track 0 signal failed to occur (Used during Sense

Interrupt command)

Not Used Always 0

Head Select

Indicates the active high status of the

HDSEL pin at the end of the Execution Phase

D1D0 Drive Select 10

These two binary encoded bits

indicate the logical drive selected at the end of the

Execution Phase

00 e Drive 0 selected

01 e Drive 1 selected

10 e Drive 2 selected

11 e Drive 3 selected

3102 Status Register 1 (ST1)

DESC

RESET

COND

End of Track

Controller transferred the last byte of

the last sector without the TC pin becoming active

The last sector is the End of Track sector number

programmed in the Command Phase

Not Used Always 0

CRC Error

If this bit is set and bit 5 of ST2 is clear

then there was a CRC error in the Address Field of

the correct sector If bit 5 of ST2 is also set then

there was a CRC error in the Data Field

Overrun

Controller was not serviced by the mP

soon enough during a data transfer in the Execution

Phase For read operations indicates a data over-

run For write operations indicates a data underrun

Not Used Always 0

No Data

Three possible problems

1 Controller cannot find the sector specified in the

Command Phase during the execution of a Read

Write Scan or Verify command An address

mark was found however so it is not a blank disk

2 Controller cannot read any Address Fields with-

out a CRC error during a Read ID command

3 Controller cannot find starting sector during exe-

cution of Read A Track command

Not Writable

Write Protect pin is active when a

Write or Format command is issued

PC87311A Datasheet(PDF) 23 Page - National Semiconductor (TI)

PC87311A Datasheet(HTML) 23 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Descarga

Enlace URL