PC87311A datasheet(42/78 Pages) NSC

42 / 78 page

50 FDC Functional Description (Continued)

PS2 and Model 30 Modes

When in the PS2 or Model 30

modes DMA transfers with the FIFO disabled are per-

formed differently Instead of a single byte transfer mode

the FIFO will actually be enabled with THRESH e 0F (hex)

Thus DRQ will be asserted when one byte has entered the

FIFO during reads and when one byte can be written to the

FIFO during writes DRQ will be deasserted by the leading

edge of the DACK input and will be reasserted when DACK

goes inactive high This operation is very similar to Burst

mode transfer with the FIFO enabled except that DRQ is

deasserted between each byte

5322 DMA ModeFIFO Enabled

Read Data Transfers

Whenever the number of bytes in the FIFO is greater than

or equal to (16 b THRESH) a DRQ is generated This is the

trigger condition for the FIFO read data transfers from the

floppy controller to the mP

Burst Mode

DRQ will remain active until enough bytes

have been read from the controller to empty the FIFO

Non-Burst Mode

DRQ will be deasserted after each read

transfer If the FIFO is not completely empty DRQ will be

reasserted after a 350 ns delay This will allow other higher

priority DMA transfers to take place between floppy trans-

fers In addition this mode will allow the controller to work

correctly in systems where the DMA controller is put into a

read verify mode where only DACK signals are sent to the

FDC with no RD pulses This read verify mode of the DMA

controller is used in some PC software The FIFO Non-Burst

mode allows the DACK input from the DMA controller to be

strobed which will correctly clock data from the FIFO

For both the Burst and Non-Burst modes when the last byte

in the FIFO has been read DRQ will go inactive DRQ will

then be reasserted when the FIFO trigger condition is satis-

fied After the last byte of a sector has been read from the

disk DRQ is again generated even if the FIFO has not yet

reached its threshold trigger condition This will guarantee

that all the current sector bytes are read from the FIFO

before the next sector byte transfer begins

Write Data Transfers

Whenever the number of bytes in the FIFO is less than or

equal to THRESH a DRQ is generated This is the trigger

condition for the FIFO write data transfers from the mPto

the floppy controller

Burst Mode

DRQ will remain active until enough bytes

have been written to the controller to completely fill the

FIFO

Non-Burst Mode

DRQ will be deasserted after each write

transfer If the FIFO is not full yet DRQ will be reasserted

after a 350 ns delay This deassertion of DRQ will allow

other higher priority DMA transfers to take place between

floppy transfers

The FIFO has a byte counter which will monitor the number

of bytes being transferred to the FIFO during write opera-

tions for both Burst and Non-Burst modes When the last

byte of a sector is transferred to the FIFO DRQ will be

deasserted even if the FIFO has not been completely filled

In this way the FIFO will be cleared after each sector is

written Only after the floppy controller has determined that

another sector is to be written will DRQ be asserted again

Also since DRQ is deasserted immediately after the last

byte of a sector is written to the FIFO the system does not

need to tolerate any DRQ deassertion delay and is free to

do other work

DRQ Deassertion

The DACK input signal from the DMA controller may be held

active during an entire burst or it may be strobed for each

byte transferred during a read or write operation If DACK is

strobed for each byte the leading edge of this strobe is

used to deassert DRQ If DACK is strobed RD or WR are

not required This is the case during the Read-Verify mode

of the DMA controller If DACK is held active during the

entire burst the leading edge of the RD or WR strobe is

used to deassert DRQ

Overrun Errors

An overrun or underrun error will terminate the execution of

the command if the system does not transfer data within the

allotted data transfer time (see Section 37) which will put

the controller into the Result Phase During a read overrun

the mP is required to read the remaining bytes of the sector

before the controller will assert IRQ6 signifying the end of

execution During a write operation an underrun error will

terminate the Execution Phase after the controller has writ-

ten the remaining bytes of the sector with the last correctly

written byte to the FIFO and generated the CRC bytes

Whether there is an error or not an interrupt is generated at

the end of the Execution Phase and is cleared by reading

the first Result Phase byte

DACK asserted by itself without a RD or WR strobe is also

counted as a transfer If RD or WR are not being strobed for

each byte then DACK must be strobed for each byte so that

the floppy controller can count the number of bytes correct-

ly A new command the Verify command has been added

to allow easier verification of data written to the disk without

the need of actually transferring the data on the data bus

5323 Interrupt ModeFIFO Disabled

If the Interrupt (Non-DMA) mode is selected IRQ6 is assert-

ed instead of DRQ when each byte is ready to be trans-

ferred The Main Status Register should be read to verify

that the interrupt is for a data transfer The RQM and NON

DMA bits (D7 and D5) in the MSR will be set The interrupt

will be cleared when the byte is transferred to or from the

Data Register CS and RD or CS and WR must be used to

transfer the data in or out of the Data Register (A2 – A0 must

be valid) CS asserted by itself is not significant CS must be

asserted with RD or WR for a read or write transfer to be

recognized

The mP should transfer the byte within the data transfer

service time (see Section 37) If the byte is not transferred

within the time allotted an Overrun Error will be indicated in

the Result Phase when the command terminates at the end

of the current sector

An interrupt will also be generated after the last byte is

transferred This indicates the beginning of the Result

Phase The RQM and DIO bits (D7 and D6) in the MSR will

be set and the NON DMA bit (D5) will be cleared This

interrupt is cleared by reading the first result byte

PC87311A Datasheet(PDF) 42 Page - National Semiconductor (TI)

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