PC87311A datasheet(17/78 Pages) NSC

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20 Configuration Registers (Continued)

C Or by executing the FDC Mode Command with the PTR

bit 1 e 0 (XTAL CLK) See Section 426 LOW PWR

D Or by setting Data Rate Select Register bit 6 high in the

FDC with the PTR bit 1 e 0 See Section 36 bit 6

Mode 2

The internal clocks are stopped for all enabled

functions

Note

Clocks to disabled functions are always inactive

This mode is entered by

A Clearing all FER bits for any enabled function See Sec-

tion 251 (FER bits 1 – 3)

B Or by clearing PTR bits 1 (XTAL CLK) and 2 (CSOUT

PWDN

select) and then asserting the PWDN signal low

See Section 253 PTR bits 12 and Section 10 PWDN

C Or by clearing PTR bit 1 and then setting PTR bit 0 (Pow-

er Down) high See Section 253 (PTR bits 0 and 1)

Mode 3

The external crystal is stopped and internal clocks

are stopped for all enabled functions

This mode is entered by

A Clearing all FER bits that enable the FDC UART1 and

UART2 functions See Section 251 (FER bits 1 – 3)

B Setting PTR bit 1 (XTAL CLK)

clearing PTR bit 2

(CSOUT PWDN select) and then asserting the PWDN

signal low See Section 253 PTR bits 12 and Section

10 PWDN pin

C Or by setting PTR bit 1 and then setting PTR bit 0 high

See Section 253 PTR bits 0 and 1

D Or during reset by pulling CFG0 – 4 pins high

E Or by executing the FDC Mode Command with the PTR

bit 1 e 1 See Section 426 LOW PWR

F Or by setting Data Rate Select Register bit 6 high in the

FDC with the PTR bit 1 e 1 See Section 36 bit 6

27 POWER-UP PROCEDURE AND CONSIDERATIONS

271 Crystal Stabilization

If the crystal is stopped by putting either the FDC or the

UARTs into low power mode then a finite amount of time

(E8 ms) must be allowed for crystal stabilization during

subsequent power-up

The stabilization period can be

sensed by reading the Main Status Register in the FDC if

the FDC is being powered up (The Request for Master bit

will not be set for E8 ms) If either one of the UARTs are

being powered up but the FDC is not then the software

must determine the E8 ms crystal stabilization period Sta-

bilization of the crystal can also be sensed by putting the

UART into local loopback mode and sending bytes until

they are received correctly

272 UART Power-Up

The clock signal to the UARTs is controlled through the

Configuration Registers (FER PTR) In order to restore the

clock signal to one or both UARTs the following conditions

must exist

1 The appropriate enable bit (FER12) for the UART(s)

must be set

2 and the Power Down bit (PTR0) must not be set

3 and if the PWDN pin option (PTR2) is used the CSOUT

PDWN pin must be inactive

If the crystal has been stopped follow the guidelines in Sec-

tion 271 before sending data or signaling that the receiver

channel is ready

273 FDC Power-Up

The clock signal to the FDC is controlled through the Con-

figuration Registers the FDC Mode Command and the Data

Rate Select Register In order to restore the clock signal to

the FDC the following conditions must exist

1 The appropriate enable bit (FER3) must be set

2 and the Power Down bit (PTR0) must not be set

3 and if the PWDN pin option (PTR2) is used the CSOUT

PDWN pin must be inactive

In addition to these conditions one of the following must be

done to initiate the recovery from Power Down mode

1 Read the Main Status Register until the ROM bit (MSR7)

is set

2 or write to the Data Rate Select Register and set the

Software Reset bit (DSR7)

3 or write to the Digital Output Register and set and then

the clear Reset bit (DOR2)

4 or read the Data Register and the Main Status Register

until the ROM bit is set

If the crystal has been stopped read the RQM bit in the

Main Status Register until it is set The RQM bit does not get

set until the crystal has stabilized

30 FDC Register Description

The floppy disk controller is suitable for all PC-AT EISA

PS2 and general purpose applications The operational

mode (PC-AT PS2 and Model 30) of the FDC is deter-

mined by hardware strapping of the IDENT and MFM pins

DP8473 and N82077 software compatibility is provided Key

features include the 16-byte FIFO PS2 diagnostic register

support the perpendicular recording mode CMOS disk in-

terface and a high performance analog data separator

The FDC supports the standard PC data rates of 250 kbs

300 kbs and 500 kbs and 1 Mbs in MFM encoded data

mode but is no longer guaranteed through functional test-

ing to support the older FM encoded data mode Refer-

ences to the older FM mode remain in this document to

clarify the true functional operation of the device

The 1 Mbs data rate is used by new high performance tape

and floppy drives emerging in the PC market today The new

floppy drives utilize high density media which requires the

FDC supported perpendicular recording mode format When

used with the 1 Mbs data rate this new format allows the

use of 4 MB floppy drives which format ED media to 288

MB data capacity

The high performance internal analog data separator needs

no external components It improves on the window margin

performance standards of the DP8473 and is compatible

with the strict data separator requirements of floppy and

floppy-tape drives

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