PC87311A datasheet(61/78 Pages) NSC

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70 Parallel Port (Continued)

NOTE Normally when the Control Register is read the bit values are

provided by the internal output data latch These bit values can be

superseded by the logic level of the STB AFD INIT and SLIN pins if

these pins are forced high or low by an external voltage In order to

force these pins high or low the corresponding bits should be set to

their inactive state (eg AFD e STB e SLIN e 0 INIT e 1)

80 Integrated Device Electronics

Interface (IDE)

81 INTRODUCTION

Another key interface design facilitated through the use of

the PC87311A12 is the IDE (Intelligent Drive Electronics)

Hard Disk interface Only three buffer chips are required to

construct the IDE Hard Disk Interface circuit (see

Figure

10-3 )

The IDE interface is essentially the AT bus ported to the

hard drive The hard disk controller resides on the hard drive

itself So the IDE interface circuit must provide the AT bus

signals including data bits D15 – D0 address lines A3 – A0

as well as the common control signals These signals are

shown on the 40-pin IDE interface header (see

Figure

10-3 )

82 IDE SIGNALS

Looking at the IDE interface circuit in more detail the

’LS244 provides buffering of the control and address lines

There are four control signals IDEHI IDELO HCS0 HCS1

one status signal IOCS16 and one data signal IDED7 re-

quired by the IDE interface The PC87311A12 provides all

of these signals They are summarized below

IDEHI enables the ’LS245 octal bus transceiver for the up-

per data lines (D15 – D8) during 16-bit read and write opera-

tions at addresses 1F0 – 1F7 IDEHI will activate the ’LS245

only if the IOCS16 output from the hard drive is active IDLO

enables the other ’LS245 octal bus transceiver for the lower

data lines (D7 – D0) during all (1F0 – 1F7 3F6 and 3F7)

reads and writes The IDED7 signal insures that the D7 data

bus signal line is disabled for address 3F7 (this bit is used

for the Disk Changed register on the floppy disk controller at

that address) The two ’LS245 chips are used to enable or

TRI-STATE the data bus signals In the PC-AT mode the

PC87311A12 provides the two hard disk chip selects

(HCS0 HCS1) for the IDE interface The HCS0 output is

active low when the 1F0 – 1F7 (hex) IO address space is

chosen and corresponds to the 1FX signal on the IDE head-

er The HCS1 output is active low when the 3F6 or 3F7 IO

addresses are chosen and corresponds to 3FX on the IDE

header These are the two address blocks used in the

PC-AT hard disk controller The table below summarizes the

addresses used by the PC-AT hard disk controller

TABLE 8-1 IDE Registers and Their ISA Addresses

Address

Read Function

Write Function

1F0

Data

1F1

Error

Features

(Write Precomp)

1F2

Sector Count

1F3

Sector Number

1F4

Cylinder Low

1F5

Cylinder High

1F6

DriveHead

1F7

Status

Command

3F6

Alternate Status

Device Control

3F7

Drive Address

Not Used

(Note)

Data Bus TRI-STATE

Note

Data bus bit D7 is dedicated to the floppy disk controller at this ad-

dress When reading this address the floppy disk controller disk change

status will be provided by bit D7 There is no write function at this address in

the IDE associated with this bit

The equations shown in

Figure 10-2 define the signals of

the PC87311A12 IDE pins A complete IDE interface using

these pins is shown in

Figure 10-3

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