PC87311A datasheet(12/78 Pages) NSC

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20 Configuration Registers

21 OVERVIEW

Three registers constitute the Base Configuration Register

set which controls the set-up of the PC87311A12 In gen-

eral these registers control the enabling of each major

function (eg FDC UARTs parallel port etc) the IO ad-

dresses of those functions and whether those functions

power down via hardware control or not These three con-

figuration registers are called the Function Enable Register

(FER) the Function Address (FAR) Register and the Power

and Test Register (PTR)

These registers can be accessed via hardware or software

During reset the PC87311A12 loads a set of default val-

ues selected by a hardware strapping option into the Config-

uration Registers This defines the setting of all Configura-

tion Registers via hardware

An index and data register pair are used to read and write

these registers Each Configuration Register is pointed to by

the value loaded into the Index Register The data to be

written into the Configuration Register is transferred via the

Data register Reading a Configuration Register is done in a

similar way (ie by pointing to it via the Index Register and

then reading its contents via the Data Register)

Accessing the Configuration Registers in this way requires

only two system IO addresses Since that IO space is

shared by other devices the Index and Data Registers could

still be inadvertantly accessed even though there are only

two registers in this IO address space In order to reduce

the chances of an inadvertant access a simple procedure

(Section 22) has been developed

22 SOFTWARE CONFIGURATION

If the system requires access to the Configuration Registers

after reset then the following procedure is used to change

data in the registers

1 Determine the default location of the PC87311A12 In-

dex Register

A Check the two possible default locations (see Table

2-2) by reading them twice The first byte is the ID byte

(88H) The second byte read is always 00H Compare

the data read with the ID byte and then 00h A match

will occur at the correct location Note that the ID byte

is only issued from the Index Register during the first

read after a reset Subsequent reads return the value

loaded into the Index Register Bits 2 – 6 are reserved

and always read 0

2 Load the Configuration Registers

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

02h) to the Index Register one time

C Write the correct data for the Configuration Register in

two consecutive write accesses to the Data Register

D Enable CPU interrupts

3 Load the Configuration Registers (read-modify-write)

A Disable CPU interrupts

B Write the index of the Configuration Register (00h –

02h) to the Index Register one time

C Read the configuration data in that register via the

Data Register

D Modify the configuration data

E Write the changed data for the Configuration Register

in two consecutive writes to the Data Register The

F Enable CPU interrupts

A single read access to the Index and Data Registers can

be done at any time without disabling CPU interrupts When

the Index Register is read the last value loaded into the

Index Register will be returned When the Data Register is

read the Configuration Register data pointed to by the In-

dex Register will be returned

TLF11362 – 38

TLF11362 – 39

TLF11362 – 40

FIGURE 2-1 PC87311A12 Configuration Registers

23 HARDWARE CONFIGURATION

During reset 1 of 32 possible sets of default values are

loaded into the Configuration Registers A strapping option

on five pins (CFG0 – 4) selects the set of values that is load-

ed This allows for automatic configuration without software

intervention Table 2-1 shows the 32 possible default con-

figurations The default configuration can be modified by

software at any time after reset by using the access proce-

dure described in the Software Configuration Section

PC87311A Datasheet(PDF) 12 Page - National Semiconductor (TI)

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