PC87311A datasheet(47/78 Pages) NSC

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50 FDC Functional Description (Continued)

288M drives since the preamble must be pre-erased be-

fore it is rewritten WGATE should be asserted when the

pre-erase head is located at the beginning of the Data Field

preamble This means that WGATE should be asserted

when the readwrite head is at least 38 bytes (at 1 Mbs)

before the preamble See Table 4-4 for a description of the

WGATE timing for perpendicular drives at the various data

rates

Because of the 38 byte spacing between the readwrite

head and the pre-erase head at 2 Mbs the GAP2 length of

22 bytes used in the standard IBM disk format is not long

enough There is a new format standard for 288M drives at

1 Mbs called the Perpendicular Format which increases

the GAP2 length to 41 bytes (see

Figure 4-1 )

The Perpendicular Mode command will put the floppy con-

troller into perpendicular recording mode which allows it to

read and write perpendicular media Once this command is

invoked the read write and format commands can be exe-

cuted in the normal manner The perpendicular mode of the

floppy controller will work at all data rates adjusting the

format and write data parameters accordingly See Section

428 for more details

57 DATA RATE SELECTION

The data rate can be chosen two different ways with the

FDC For PC compatible software the Configuration Control

rate for the floppy controller The lower bits D1 and D0 are

used in the CCR to set the data rate The other bits should

be set to zero See Table 3-6 for the data rate select encod-

ing

The data rate can also be set using the Data Rate Select

ter are used to set the data rate The encoding of these bits

is exactly the same as those in the CCR The remainder of

the bits in the DSR are used for other functions Consult the

The data rate is determined by the last value that is written

to either the CCR or the DSR In other words either the

CCR or the DSR can override the data rate selection of the

other register When the data rate is selected the micro-

engine and data separator clocks are scaled appropriately

Also the DRATE0 and DRATE1 output pins will reflect the

state of the data select bits that were last written to either

the CCR or the DSR

58 WRITE PRECOMPENSATION

Write precompensation is a way of preconditioning the

WDATA output signal to adjust for the effects of bit shift on

the data as it is written to the disk surface Bit shift is caused

by the magnetic interaction of data bits as they are written

to the disk surface and has the effect of shifting these data

bits away from their nominal position in the serial MFM or

FM data pattern Data that is subject to bit shift is much

harder to read by a data separator and can cause soft read

errors Write precompensation predicts where bit shift could

occur within a data pattern It then shifts the individual data

bits early late or not at all such that when they are written

to the disk the resultant shifted data bits will be back in their

nominal position

The FDC supports software programmable write precom-

pensation Upon power up the default write precomp values

will be used (see Table 3-5) The programmer can choose a

different value of write precomp with the DSR register if

desired (see Table 3-4) Also on power up the default start-

ing track number for write precomp is track zero This start-

ing track number for write precomp can be changed with the

Configure command

59 FDC LOW POWER MODE LOGIC

The FDC section of the PC87311A12 supports two low

power modes described here in detail Other low power

modes of the PC87311A12 described in Section 26 are

covered below and in section 36 and 426 The microcode

is driven from the clock so it will be disabled while the clock

is off The FDC clock is always disabled upon entering this

mode however the oscillator is only disabled when PTR1

1 Upon entering the power down state the RQM (Re-

quest For Master) bit in the MSR will be cleared

There are two modes of low power in the floppy controller

manual low power and automatic low power Manual low

power is enabled by writinga1tobit6ofthe DSR The chip

will go into low power immediately This bit will be cleared to

0 after the chip is brought out of low power Manual low

power can also be accessed via the Mode command The

function of the manual low power mode is a logical OR func-

tion between the DSR low power bit and the Mode com-

mand manual low power bit setting

Automatic low power mode will switch the controller into low

power 500 ms (at the 500 kbs MFM data rate) after it has

entered the idle state Once the auto low power mode is set

it does not have to be set again and the controller will auto-

matically go into low power mode after it has entered the

idle state Automatic low power mode can only be set with

the Mode command

There are two ways the FDC section can recover from the

power down state The part will power up after a software

reset via the DOR or DSR Since a software reset requires

reinitialization of the controller this method can be undesir-

able The part will also power up after a read or write to

either the Data Register or Main Status Register This is the

preferred method of power up since all internal register val-

ues are retained It may take a few milliseconds for the os-

cillator to stabilize and the mP will be prevented from issu-

ing commands during this time through the normal Main

Status Register protocol That is the RQM bit in the MSR

will be a 0 until the oscillator has stabilized When the con-

troller has completely stabilized from power up the RQM bit

in the MSR is set to 1 and the controller can continue where

it left off

The Data Rate Select Digital Output and Configuration

Control Registers are unaffected by the power down mode

They will remain active It is up to the user to ensure that the

Motor and Drive Select signals are turned off

Note

If the power to an external oscillator driving the PC87311A12 is to be

independently removed during the FDC low power mode it must not

be done until 2 ms after the FDC low power command is issued

510 RESET OPERATION

The floppy controller can be reset by hardware or software

Hardware reset is enacted by pulsing the Master Reset in-

put pin A hardware reset will set all of the user addressable

registers and internal registers to their default values The

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