PC87311A datasheet(43/78 Pages) NSC

43 / 78 page

50 FDC Functional Description (Continued)

5324 Interrupt ModeFIFO Enabled

The Interrupt (Non-DMA) mode with the FIFO enabled is

very similar to the Non-DMA mode with the FIFO disabled

In this case IRQ6 is asserted instead of DRQ under the

exact same FIFO threshold trigger conditions The MSR

should be read to verify that the interrupt is for a data trans-

fer The RQM and NON DMA bits (D7 and D5) in the MSR

will be set CS and RD or CS and WR must be used to

transfer the data in or out of the Data Register (A2 – A0 must

be valid) CS asserted by itself is not significant CS must be

asserted with RD or WR for a read or write transfer to be

recognized

The Burst mode may be used to hold the IRQ6 pin active

during a burst or the Non-Burst mode may be used to tog-

gle the IRQ6 pin for each byte of a burst The Main Status

ample during a read command after the last byte of data

has been read from the disk and placed in the FIFO the

MSR will still indicate that the Execution Phase is active

and that data needs to be read from the Data Register Only

after the last byte of data has been read by the mP from the

FIFO will the Result Phase begin

The same overrun and underrun error procedures from the

DMA mode apply to the Non-DMA mode Also whether

there is an error or not an interrupt is generated at the end

of the Execution Phase and is cleared by reading the first

Result Phase byte

5325 Software Polling

If the Non-DMA mode is selected and interrupts are not

suitable the mP can poll the MSR during the Execution

Phase to determine when a byte is ready to be transferred

The RQM bit (D7) in the MSR reflects the state of the IRQ6

signal Otherwise the data transfer is similar to the Interrupt

Mode described above This is true for the FIFO enabled or

disabled

533 Result Phase

During the Result Phase the mP reads a series of bytes

from the data register These bytes indicate the status of the

command This status may indicate whether the command

executed properly or contain some control information (see

the Command Description Table and Status Register De-

scription) These Result Phase bytes are read in the order

specified for that particular command Some commands will

not have a result phase Also the number of result bytes

varies with each command All of the result bytes must be

read from the Data Register before the next command can

be issued

Like the Command Phase the Main Status Register con-

trols the flow of result bytes and must be polled by the

software before reading each Result Phase byte from the

Data Register The RQM bit (D7) and DIO bit (D6) must both

be set before each result byte can be read After the last

result byte is read the COM PROG bit (D4) in the MSR will

be cleared and the controller will be ready for the next com-

mand

534 Idle Phase

After a hardware or software reset or after the chip has

recovered from the power down mode the controller enters

the Idle Phase Also when there are no commands in prog-

ress the controller will be in the Idle Phase The controller

will be waiting for a command byte to be written to the Data

cleared in the MSR After receiving the first command (op-

code) byte the controller will enter the Command Phase

When the command is completed the controller again en-

ters the Idle Phase The Data Separator will remain synchro-

nized to the reference frequency while the controller is idle

While in the Idle Phase the controller will periodically enter

the Drive Polling Phase (see below)

535 Drive Polling Phase

While in the Idle Phase the controller will enter a Drive Poll-

ing Phase every 1 ms (based on the 500 kbs data rate)

While in the Drive Polling Phase the controller will interro-

gate the Ready Changed status for each of the four logical

drives The internal Ready changed status for each drive is

toggled only after a hardware or software reset and an in-

terrupt will be generated for drive 0 At this point the soft-

ware must issue four Sense Interrupt commands to clear

the Ready Changed State status for each drive This re-

quirement can be eliminated if drive polling is disabled via

the POLL bit in the Configure command The Configure

command must be issued within 500 ms (worst case ) of the

hardware or software reset for drive polling to be disabled

The controller uses the Drive Polling Phase to control the

Automatic Low Power mode Even if drive polling is dis-

abled drive stepping and delayed power down will occur in

the Drive Polling Phase The controller will check the status

of each drive and if necessary it will issue a step pulse on

the STEP output with the DIR signal at the appropriate logic

level When the Motor Off time has expired the controller

will wait 512 ms based on the 500 kbs and 1 Mbs data

rate before automatic powering down if this function is en-

abled via the Mode command

54 DATA SEPARATOR

The internal data separator consists of an analog PLL and

its associated circuitry The PLL synchronizes the raw data

signal read from the disk drive The synchronized signal is

used to separate the encoded clock and data pulses The

data pulses are deserialized into bytes and then sent to the

P by the controller

The main PLL consists of five main components a phase

comparator a charge pump a filter a voltage controlled

oscillator (VCO) and a programmable divider The phase

comparator detects the difference between the phase of the

divider’s output and the phase of the raw data being read

from the disk This phase difference is converted to a cur-

rent by the charge pump which either charges or discharg-

es one of three filters which is selected based on the data

rate The resulting voltage on the filter changes the frequen-

cy of the VCO and the divider output to reduce the phase

difference between the input data and the divider’s output

The PLL is ‘‘locked’’ when the frequency of the divider is

exactly the same as the average frequency of the data read

from the disk A block diagram of the data separator is

shown in

Figure 5-1

To ensure optimal performance the data separator incorpo-

rates several additional circuits The quarter period delay

line is used to determine the center of each bit cell and to

disable the phase comparator when the raw data signal is

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