PIC17C44 datasheet(95/241 Pages) MICROCHIP

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DS30412C-page 95

PIC17C4X

13.3.2

USART SYNCHRONOUS MASTER

RECEPTION

Once synchronous mode is selected, reception is

enabled by setting either the SREN (RCSTA<5>) bit or

the CREN (RCSTA<4>) bit. Data is sampled on the

RA4/RX/DT pin on the falling edge of the clock. If

SREN is set, then only a single word is received. If

CREN is set, the reception is continuous until CREN is

reset. If both bits are set, then CREN takes prece-

dence. After clocking the last bit, the received data in

the Receive Shift Register (RSR) is transferred to

RCREG (if it is empty). If the transfer is complete, the

interrupt bit RCIF (PIR<0>) is set. The actual interrupt

can

enabled/disabled

setting/clearing

the

RCIE (PIE<0>) bit. RCIF is a read only bit which is

RESET by the hardware. In this case it is reset when

RCREG has been read and is empty. RCREG is a dou-

ble buffered register; i.e., it is a two deep FIFO. It is

possible for two bytes of data to be received and trans-

ferred to the RCREG FIFO and a third byte to begin

shifting into the RSR. On the clocking of the last bit of

the third byte, if RCREG is still full, then the overrun

error bit OERR (RCSTA<1>) is set. The word in the

RSR will be lost. RCREG can be read twice to retrieve

the two bytes in the FIFO. The OERR bit has to be

cleared in software. This is done by clearing the CREN

bit. If OERR bit is set, transfers from RSR to RCREG

are inhibited, so it is essential to clear OERR bit if it is

set. The 9th receive bit is buffered the same way as the

receive data. Reading the RCREG register will allow

the RX9D and FERR bits to be loaded with values for

the next received data; therefore, it is essential for the

user to read the RCSTA register before reading

RCREG in order not to lose the old FERR and RX9D

information.

Steps to follow when setting up a Synchronous Master

Reception:

Initialize the SPBRG register for the appropriate

baud rate. See Section 13.1 for details.

Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

If interrupts are desired, then set the RCIE bit.

If 9-bit reception is desired, then set the RX9 bit.

If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

The RCIF bit will be set when reception is com-

plete and an interrupt will be generated if the

RCIE bit was set.

Read RCSTA to get the ninth bit (if enabled) and

determine if any error occurred during reception.

Read the 8-bit received data by reading

RCREG.

If any error occurred, clear the error by clearing

CREN.

Note:

To terminate a reception, either clear the

SREN and CREN bits, or the SPEN bit.

This will reset the receive logic, so that it

will be in the proper state when receive is

re-enabled.

FIGURE 13-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

CREN bit

Write to the

SREN bit

RCIF bit

Read

RCREG

Note: Timing diagram demonstrates SYNC master mode with SREN = 1.

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

'0'

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

'0'

Q1 Q2 Q3 Q4

(RA4/RX/DT pin)

(RA5/TX/CK pin)

PIC17C44 Datasheet(PDF) 95 Page - Microchip Technology

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