PIC17C44 datasheet(78/241 Pages) MICROCHIP

78 / 241 page

PIC17C4X

DS30412C-page 78

12.2.1

ONE CAPTURE AND ONE PERIOD

In this mode registers PR3H/CA1H and PR3L/CA1L

constitute a 16-bit period register. A block diagram is

shown in Figure 12-7. The timer increments until it

equals the period register and then resets to 0000h.

TMR3 Interrupt Flag bit (TMR3IF) is set at this point.

This interrupt can be disabled by clearing the TMR3

Interrupt Enable bit (TMR3IE). TMR3IF must be

cleared in software.

This mode is selected if control bit CA1/PR3 is clear. In

this mode, the Capture1 register, consisting of high

byte (PR3H/CA1H) and low byte (PR3L/CA1L), is con-

ﬁgured as the period control register for TMR3.

Capture1 is disabled in this mode, and the correspond-

ing Interrupt bit CA1IF is never set. TMR3 increments

until it equals the value in the period register and then

resets to 0000h.

Capture2 is active in this mode. The CA2ED1 and

CA2ED0 bits determine the event on which capture will

occur. The possible events are:

• Capture on every falling edge

• Capture on every rising edge

• Capture every 4th rising edge

• Capture every 16th rising edge

When a capture takes place, an interrupt ﬂag is latched

into the CA2IF bit. This interrupt can be enabled by set-

ting the corresponding mask bit CA2IE. The Peripheral

Interrupt Enable bit (PEIE) must be set and the Global

Interrupt Disable bit (GLINTD) must be cleared for the

interrupt to be acknowledged. The CA2IF interrupt ﬂag

bit must be cleared in software.

When the capture prescale select is changed, the pres-

caler is not reset and an event may be generated.

Therefore, the ﬁrst capture after such a change will be

ambiguous. However, it sets the time-base for the next

capture. The prescaler is reset upon chip reset.

Capture pin RB1/CAP2 is a multiplexed pin. When used

as a port pin, Capture2 is not disabled. However, the

user can simply disable the Capture2 interrupt by clear-

ing CA2IE. If RB1/CAP2 is used as an output pin, the

user can activate a capture by writing to the port pin.

This may be useful during development phase to emu-

late a capture interrupt.

The input on capture pin RB1/CAP2 is synchronized

internally to internal phase clocks. This imposes certain

restrictions on the input waveform (see the Electrical

Speciﬁcation section for timing).

The Capture2 overﬂow status ﬂag bit is double buff-

ered. The master bit is set if one captured word is

already residing in the Capture2 register and another

“event” has occurred on the RB1/CA2 pin. The new

event will not transfer the Timer3 value to the capture

When the user reads both the high and the low bytes (in

any order) of the Capture2 register, the master overﬂow

bit is transferred to the slave overﬂow bit (CA2OVF) and

then the master bit is reset. The user can then read

TCON2 to determine the value of CA2OVF.

The recommended sequence to read capture registers

and

capture

overﬂow

ﬂag

bits

shown

Example 12-1.

EXAMPLE 12-1: SEQUENCE TO READ

CAPTURE REGISTERS

MOVLB 3

;Select Bank 3

MOVPF CA2L,LO_BYTE

;Read Capture2 low

;byte, store in LO_BYTE

MOVPF CA2H,HI_BYTE

;Read Capture2 high

;byte, store in HI_BYTE

MOVPF TCON2,STAT_VAL ;Read TCON2 into file

;STAT_VAL

FIGURE 12-7: TIMER3 WITH ONE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM

PR3H/CA1H

TMR3H

Comparator<8>

Fosc/4

TMR3ON

Reset

Equal

Comparator x16

RB5/TCLK3

Set TMR3IF

TMR3CS

PR3L/CA1L

TMR3L

CA2H

CA2L

RB1/CAP2

Edge select

prescaler select

Set CA2IF

Capture1 Enable

CA2ED1: CA2ED0

(TCON1<7:6>)

(TCON2<2>)

(TCON1<2>)

(PIR<3>)

(PIR<6>)

PIC17C44 Datasheet(PDF) 78 Page - Microchip Technology

PIC17C44 Datasheet(HTML) 78 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL