PIC17C44 datasheet(89/241 Pages) MICROCHIP

89 / 241 page

DS30412C-page 89

PIC17C4X

13.2

USART Asynchronous Mode

In this mode, the USART uses standard nonre-

turn-to-zero (NRZ) format (one start bit, eight or nine

data bits, and one stop bit). The most common data for-

mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-

erator can be used to derive standard baud rate

frequencies from the oscillator. The USART’s transmit-

ter and receiver are functionally independent but use

the same data format and baud rate. The baud rate

generator produces a clock x64 of the bit shift rate. Par-

ity is not supported by the hardware, but can be imple-

mented in software (and stored as the ninth data bit).

Asynchronous mode is stopped during SLEEP.

The asynchronous mode is selected by clearing the

SYNC bit (TXSTA<4>).

The USART Asynchronous module consists of the fol-

lowing important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

13.2.1

USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in

Figure 13-3. The heart of the transmitter is the transmit

shift register (TSR). The shift register obtains its data

from the read/write transmit buffer (TXREG). TXREG is

loaded with data in software. The TSR is not loaded

until the stop bit has been transmitted from the previous

load. As soon as the stop bit is transmitted, the TSR is

loaded with new data from the TXREG (if available).

Once TXREG transfers the data to the TSR (occurs in

one TCY at the end of the current BRG cycle), the

TXREG is empty and an interrupt bit, TXIF (PIR<1>) is

set. This interrupt can be enabled or disabled by the

TXIE bit (PIE<1>). TXIF will be set regardless of TXIE

and cannot be reset in software. It will reset only when

new data is loaded into TXREG. While TXIF indicates

the status of the TXREG, the TRMT (TXSTA<1>) bit

shows the status of the TSR. TRMT is a read only bit

which is set when the TSR is empty. No interrupt logic

is tied to this bit, so the user has to poll this bit in order

to determine if the TSR is empty.

Note:

The TSR is not mapped in data memory,

so it is not available to the user.

Transmission

enabled

setting

the

TXEN (TXSTA<5>) bit. The actual transmission will not

occur until TXREG has been loaded with data and the

baud rate generator (BRG) has produced a shift clock

(Figure 13-5). The transmission can also be started by

ﬁrst loading TXREG and then setting TXEN. Normally

when transmission is ﬁrst started, the TSR is empty, so

a transfer to TXREG will result in an immediate transfer

to TSR resulting in an empty TXREG. A back-to-back

transfer is thus possible (Figure 13-6). Clearing TXEN

during a transmission will cause the transmission to be

aborted. This will reset the transmitter and the

RA5/TX/CK pin will revert to hi-impedance.

order

select

9-bit

transmission,

the

TX9 (TXSTA<6>) bit should be set and the ninth bit

should be written to TX9D (TXSTA<0>). The ninth bit

must be written before writing the 8-bit data to the

TXREG. This is because a data write to TXREG can

result in an immediate transfer of the data to the TSR

(if the TSR is empty).

Steps to follow when setting up an Asynchronous

Transmission:

Initialize the SPBRG register for the appropriate

baud rate.

Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

If interrupts are desired, then set the TXIE bit.

If 9-bit transmission is desired, then set the TX9

bit.

Load data to the TXREG register.

If 9-bit transmission is selected, the ninth bit

should be loaded in TX9D.

Enable the transmission by setting TXEN (starts

transmission).

Writing the transmit data to the TXREG, then enabling

the transmit (setting TXEN) allows transmission to start

sooner then doing these two events in the opposite

order.

Note:

To terminate a transmission, either clear

the SPEN bit, or the TXEN bit. This will

reset the transmit logic, so that it will be in

the

proper

state

when

transmit

re-enabled.

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