| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
PIC17C44 Datasheet(PDF) 83 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC17C44 Datasheet(HTML) 83 Page - Microchip Technology |
|
83 / 241 page ![]() © 1996 Microchip Technology Inc. DS30412C-page 83 PIC17C4X 13.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE The USART module is a serial I/O module. The USART can be configured as a full duplex asynchronous sys- tem that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) The SPEN (RCSTA<7>) bit has to be set in order to configure RA4 and RA5 as the Serial Communication Interface. The USART module will control the direction of the RA4/RX/DT and RA5/TX/CK pins, depending on the states of the USART configuration bits in the RCSTA and TXSTA registers. The bits that control I/O direction are: • SPEN • TXEN • SREN • CREN • CSRC The Transmit Status And Control Register is shown in Figure 13-1, while the Receive Status And Control Register is shown in Figure 13-2. FIGURE 13-1: TXSTA REGISTER (ADDRESS: 15h, BANK 0) R/W - 0 R/W - 0 R/W - 0 R/W - 0 U - 0 U - 0 R - 1 R/W - x CSRC TX9 TXEN SYNC — — TRMT TX9D R = Readable bit W = Writable bit -n = Value at POR reset (x = unknown) bit7 bit0 bit 7: CSRC: Clock Source Select bit Synchronous mode: 1 = Master Mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) Asynchronous mode: Don’t care bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled SREN/CREN overrides TXEN in SYNC mode bit 4: SYNC: USART mode Select bit (Synchronous/Asynchronous) 1 = Synchronous mode 0 = Asynchronous mode bit 3-2: Unimplemented: Read as '0' bit 1: TRMT: Transmit Shift Register (TSR) Empty bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data (can be used to calculated the parity in software) This document was created with FrameMaker404 |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |