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PIC17C44 Datasheet(PDF) 81 Page - Microchip Technology |
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PIC17C44 Datasheet(HTML) 81 Page - Microchip Technology |
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81 / 241 page  © 1996 Microchip Technology Inc. DS30412C-page 81 PIC17C4X FIGURE 12-10: TMR1, TMR2, AND TMR3 OPERATION IN TIMER MODE TABLE 12-6: SUMMARY OF TMR1, TMR2, AND TMR3 REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note1) 16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 10h, Bank 2 TMR1 Timer1 register xxxx xxxx uuuu uuuu 11h, Bank 2 TMR2 Timer2 register xxxx xxxx uuuu uuuu 12h, Bank 2 TMR3L TMR3 register; low byte xxxx xxxx uuuu uuuu 13h, Bank 2 TMR3H TMR3 register; high byte xxxx xxxx uuuu uuuu 16h, Bank 1 PIR RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 17h, Bank 1 PIE RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE RCIE 0000 0000 0000 0000 07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000 06h, Unbanked CPUSTA — — STKAV GLINTD TO PD — — --11 11-- --11 qq-- 14h, Bank 2 PR1 Timer1 period register xxxx xxxx uuuu uuuu 15h, Bank 2 PR2 Timer2 period register xxxx xxxx uuuu uuuu 16h, Bank 2 PR3L/CA1L Timer3 period/capture1 register; low byte xxxx xxxx uuuu uuuu 17h, Bank 2 PR3H/CA1H Timer3 period/capture1 register; high byte xxxx xxxx uuuu uuuu 10h, Bank 3 PW1DCL DC1 DC0 — — — — — — xx-- ---- uu-- ---- 11h, Bank 3 PW2DCL DC1 DC0 TM2PW2 — — — — — xx0- ---- uu0- ---- 12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 14h, Bank 3 CA2L Capture2 low byte xxxx xxxx uuuu uuuu 15h, Bank 3 CA2H Capture2 high byte xxxx xxxx uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by TMR1, TMR2 or TMR3. Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset. Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 AD15:AD0 ALE Instruction fetched TMR1 PR1 TMR1ON WR_TMR1 WR_TCON2 TMR1IF RD_TMR1 TMR1 reads 03h TMR1 reads 04h MOVWF TMR1 Write TMR1 MOVF TMR1, W Read TMR1 MOVF TMR1, W Read TMR1 BSF TCON2, 0 Stop TMR1 BCF TCON2, 0 Start TMR1 MOVLB 3 NOP NOP NOP NOP NOP 04h 05h 03h 04h 05h 06h 07h 08h 00h |
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