CC1150-RTR1 datasheet(26/67 Pages) TI

26 / 67 page

CC1150

SWRS037A

Page 26 of 60

When for example a 600-byte packet is to be

transmitted, the MCU should do the following

(see also Figure 14):

•

Set PKTCTRL0.LENGTH_CONFIG=2.

•

Pre-program the PKTLEN register to

mod(600,256)=88

•

Transmit at least 345 bytes, for example

by filling the 64-byte TX FIFO six times

(384 bytes transmitted).

•

Set PKTCTRL0.LENGTH_CONFIG=0.

•

The transmission ends when the packet

counter reaches 88. A total of 600 bytes

are transmitted.

Figure 14: Arbitrary Length Field Configuration

13.3

Packet Handling in Transmit Mode

The payload that is to be transmitted must be

written into the TX FIFO. The first byte written

must be the length byte when variable packet

length is enabled. The length byte has a value

equal to the payload of the packet (including

the optional address byte). If fixed packet

length is enabled, then the first byte written to

the TX FIFO is interpreted as the destination

address, if this feature is enabled in the device

that receives the packet.

The modulator will first send the programmed

number of preamble bytes. If data is available

in the TX FIFO, the modulator will send the

two-byte (optionally 4-byte) sync word and

then the payload in the TX FIFO. If CRC is

enabled, the checksum is calculated over all

the data pulled from the TX FIFO and the

result is sent as two extra bytes at the end of

the payload data. If the TX FIFO runs empty

before

the

complete

packet

has

been

transmitted,

the

radio

will

enter

TXFIFO_UNDERFLOW state. The only way to

exit this state is by issuing an SFTX strobe.

Writing to the TX FIFO after it has underflowed

will not restart TX mode.

If whitening is enabled, the length byte,

payload data and the two CRC bytes will be

whitened. This is done before the optional

FEC/Interleaver stage. Whitening is enabled

by setting PKTCTRL0.WHITE_DATA=1.

If FEC/Interleaving is enabled, the length byte,

payload data and the two CRC bytes will be

scrambled by the interleaver, and FEC

encoded before being modulated. FEC is

enabled by setting MDMCFG1.FEC_EN=1.

13.4 Packet Handling in Firmware

When implementing a packet oriented radio

protocol in firmware, the MCU needs to know

when

packet

has

been

transmitted.

Additionally, for packets longer than 64 bytes,

the TX FIFO needs to be refilled while in TX.

This means that the MCU needs to know the

number of bytes that can be written to the TX

FIFO. There are two possible solutions to get

the necessary status information:

a) Interrupt Driven Solution

The GDO pins can be used in TX to give an

interrupt when a sync word has been

transmitted or when a complete packet has

been

transmitted

setting

IOCFGx.GDOx_CFG=0x06

. In addition, there

are

two

configurations

for

the

IOCFGx.GDOx_CFG

as an interrupt source to provide information

on how many bytes that is in the TX FIFO. The

IOCFGx.GDOx_CFG=0x02

and

the

CC1150-RTR1 Datasheet(PDF) 26 Page - Texas Instruments

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