CC1150-RTR1 datasheet(10/67 Pages) TI

10 / 67 page

CC1150

SWRS037A

Page 10 of 60

Pin Configuration

The

CC1150 pin-out is shown in Figure 1 and Table 11.

GND

Exposed die

attach pad

9CSn

10 RF_P

11 RF_N

12 AVDD

SCLK

SO (GDO1)

DVDD

DCOUPL

Figure 1: Pinout Top View

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main

ground connection for the chip.

Pin #

Pin name

Pin type

Description

SCLK

Digital Input

Serial configuration interface, clock input.

SO (GDO1)

Digital Output

Serial configuration interface, data output.

Optional general output pin when CSn is high.

DVDD

Power (Digital)

1.8 V - 3.6 V digital power supply for digital I/O’s and for the digital core

voltage regulator.

DCOUPL

Power (Digital)

1.6 V - 2.0 V digital power supply output for decoupling.

NOTE: This pin is intended for use with the

CC1150 only. It can not be used

to provide supply voltage to other devices.

XOSC_Q1

Analog I/O

Crystal oscillator pin 1, or external clock input.

AVDD

Power (Analog)

1.8 V - 3.6 V analog power supply connection.

XOSC_Q2

Analog I/O

Crystal oscillator pin 2.

GDO0

(ATEST)

Digital I/O

Digital output pin for general use:

• Test signals

• FIFO status signals

• Clock output, down-divided from XOSC

• Serial input TX data

Also used as analog test I/O for prototype/production testing.

CSn

Digital Input

Serial configuration interface, chip select.

RF_P

RF I/O

Positive RF output signal from PA.

RF_N

RF I/O

Negative RF output signal from PA.

AVDD

Power (Analog)

1.8 V - 3.6 V analog power supply connection.

AVDD

Power (Analog)

1.8 V - 3.6 V analog power supply connection.

RBIAS

Analog I/O

External bias resistor for reference current .

DGUARD

Power (Digital)

Power supply connection for digital noise isolation.

Digital Input

Serial configuration interface, data input.

Table 11: Pinout Overview

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