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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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CC1150-RTR1 Datasheet(PDF) 18 Page - Texas Instruments |
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CC1150-RTR1 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 67 page  CC1150 SWRS037A Page 18 of 60 Figure 8: SmartRF Studio User Interface 10 4-wire Serial Configuration and Data Interface CC1150 is configured via a simple 4-wire SPI- compatible interface (SI, SO, SCLK and CSn) where CC1150 is the slave. This interface is also used to read and write buffered data. All address and data transfer on the SPI interface is done most significant bit first. All transactions on the SPI interface start with a header byte containing a read/write bit, a burst access bit and a 6-bit address. During address and data transfer, the CSn pin (Chip Select, active low) must be kept low. If CSn goes high during the access, the transfer will be cancelled. The timing for the address and data transfer on the SPI interface is shown in Figure 9 with reference to Table 15. When CSn is pulled low, the MCU must wait until the CC1150 SO pin goes low before starting to transfer the header byte. This indicates that the voltage regulator has stabilized and the crystal is running. Unless the chip is in the SLEEP or XOFF states, the SO pin will always go low immediately after taking CSn low. |
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