LAN8804SLASHZMXC1 datasheet(16/91 Pages) MICROCHIP

16 / 91 page

LAN8804

DS00003591G-page 16

TABLE 3-4:

SYSTEM CLOCK PINS

Name

Symbol

Buffer

Type

Description

Crystal Input /

System

Reference Clock

Input

ICLK

When using a 25 MHz crystal, this input is connected to one

lead of the crystal. Refer to

REF_CLK_SEL[1:0] for additional

information.

When using a 25 MHz system reference clock, this is the input

from the external 25 MHz oscillator.

Crystal Output

OCLK

When using a 25 MHz crystal, this output is connected to one

lead of the crystal. Refer to

REF_CLK_SEL[1:0] for additional

information.

When using a 25 MHz system reference clock source, this pin

is not connected.

System

Reference Clock

Input Positive

CK125_REF_INP

LVDS1

Positive signal of differential pair. When using a 125 MHz sys-

tem reference clock source, this is connected to the external

125 MHz oscillator. Refer to

REF_CLK_SEL[1:0] for additional

information.

System

Reference Clock

Input Negative

CK125_REF_INM

LVDS1

Negative signal of differential pair. When using a 125 MHz sys-

tem reference clock source, this is connected to the external

125 MHz oscillator. Refer to

REF_CLK_SEL[1:0] for additional

information.

System Clock

Output

CK25OUT

OCLK

Buffered copy of internal 25 MHz reference clock. This output

clock is powered by

VDDAH.

TABLE 3-5:

MISCELLANEOUS PINS

Name

Symbol

Buffer

Type

Description

Management

Interface Data

MDIO

VIS/

VO12

VOD12

PHY Management data interface.

Note:

An external pull-up resistor to

VDDIO in the range of

1.0 kΩ to 4.7 kΩ is required (1.0 kΩ for high-speed

MDIO operation).

The buffer type (push-pull or open-drain/open-source)

depends on the setting of the MDIO Buffer Type bit in the Out-

put Control register, as well as the disable_mdo_drv bit in each

port’s direct register 17.

See Section 5.14.1, High-Speed MDIO Operation for addi-

tional details.

Management

Interface Clock

MDC

VIS

PHY Management clock input.

PHY Interrupt

INT_N

VO12/

VOD12

(PU)

Programmable interrupt output.

The buffer type (push-pull or open-drain) depends on the set-

ting of the INT Buffer Type bit in the Output Control register

and defaults to open-drain.

The polarity depends on the setting of the Intr Polarity Invert bit

in the Control register and defaults to active low.

Start of Frame

Ports 3-0

SOF[3:0]

SRL

RX and TX Start of Frame indicator. A pulse indicates Start of

Frame is detected on the selected transmit or receive port.

These pins can be configured via the GPIO SOF Select regis-

ter. This pin is shared with other functions.

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