LAN8804SLASHZMXC1 datasheet(86/91 Pages) MICROCHIP

86 / 91 page

LAN8804

DS00003591G-page 86

Table 1-1

Added 10BASE-Te definition.

Table 1-2, Table 3-3,

Table 3-4, Table 6-8

• Updated LVDS buffer type to LVDS1 and

LVDS2

• CLK125_REF_INP/INM assigned LVDS1,

REF_PAD_CLK_P/M assigned LVDS2

• Updated buffer characteristics to include both

LVDS1 and LVDS2

Figure 3-1, Table 3-1

Updated the following port 2 and port 3 VDDAL

ADC naming conventions to match silicon revision

B0:

•

VDDAL_ADC_D_P2/P3 changed to

VDDAL_ADC_A_P2/P3

•

VDDAL_ADC_C_P2/P3 changed to

VDDAL_ADC_B_P2/P3

•

VDDAL_ADC_B_P2/P3 changed to

VDDAL_ADC_C_P2/P3

•

VDDAL_ADC_A_P2/P3 changed to

VDDAL_ADC_D_P2/P3

Figure 3-1

Updated Pin 1 orientation

Table 3-1

Changed

MDIO and MDC pin reset states to Z

Table 3-4

Updated

CK25OUT definition to include: “This out-

put clock is powered by

VDDAH.”

Table 3-5

• Added additional information to

MDIO descrip-

tion

• Removed pull-ups on

MDIO and MDC pins

• Updated

REF_CLK_SEL[1:0] definition for 01

to “RESERVED” and added note

Table 3-7

• Added note to

PHYAD[4:0] definition:

“

PHYAD[4:0] must not be greater than ‘h1C.”

Table 3-9

• Updated “01001” definition to RESERVED

• Added legend entry to indicate what ‘X’ means

• Changed ‘y’ to ‘X’

Section 4.1, Voltage Regula-

tor and Power Connections

Corrected electrolytic capacitor value to 220 µF

Figure 4-1

• Updated to separate

VDDAL_SERDES and

VDDTXL_SERDES into two separate ferrite

beads

• Added RC circuit to

VDDAH_PLL_PTP signal

Figure 4-2

Updated to include note on external termination

resistor.

Figure 4-3

• Corrected RJ-45 pins (+/-)

• Added note under figure “The device supports

integrated connector magnetics with ganged

center taps.”

TABLE A-1:

REVISION HISTORY (CONTINUED)

Revision

Section/Figure/Entry

Correction

LAN8804/ZMXC1 Datasheet(PDF) 86 Page - Microchip Technology

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