LAN8804SLASHZMXC1 datasheet(38/91 Pages) MICROCHIP

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LAN8804

DS00003591G-page 38

5.9

IEEE 802.3-2018 Frame Preemption

IEEE Standard 802.3-2018 [1] specifies a method for interspersing express traffic by preempting the transmission of a

normal packet, transmitting the express packet and then resuming the normal packet. The receiver likewise reassem-

bles the fragmented normal packet.

The preemption and reassembly is performed using a newly defined mPacket format. This mPacket format starts with

the normal preamble but supplements the normal Start of Frame Delimiter (SFD = 0xD5) with newly defined Start

mPacket Delimiters (SMDs) of various values. Also added for certain mPackets is a fragment count octet.

If Frame Preemption is not in use, the SFD appears ahead of every Ethernet frame on the PHY port. If Frame Preemp-

tion is in use, one of several possible SMDs may appear in place of the SFD on the PHY ports. The SMD and SFD

characters are passed transparently across QSGMII (no PCH/MCH header).

Section 5.10, "Start of Frame Indication" defines SOF pulse generation support for the SMDs.

APPLICATION NOTE: Preemption is not supported at 10 Mbps.

5.10 Start of Frame Indication

The device supports the generation of an SOF pulse for the receive and transmit paths. Four SOF outputs are available,

each of which is configurable to be any of the eight available SOF pulses (TX SOF and RX SOF on each port). The SOF

pulse is generated when the Start of Frame Delimiter (SFD octet 0xD5 immediately following the preamble) is detected

by the PCS and can be output onto any enabled GPIO pin by setting the corresponding bits in the General Purpose IO

Data Select 1 register (GPIO_DATA_SEL1) or the General Purpose IO Data Select 2 register (GPIO_DATA_SEL2). The

SOF pulse is always active high. For details on SOF detection timing, refer to Section 6.6.8, "GPIO SOF Detection Tim-

ing".

The SOF pulse can also be configured to detect 802.3-2018 SMDs. When the SOF_preemption_enable bits in MMD2

continuation frame: SMD-V (0x07), SMD-R (0x19), SMD-E (0xD5) and SMD-S[0,1,2,3] (0xE6, 0x4C, 0x7F or 0xB3).

When the SOF_preemption_enable bits are set to ‘11’, the SOF pulse is also generated for the continuation SMD val-

ues: SMD-C[0,1,2,3] (0x61, 0x52, 0x9E or 0x2A).

5.11 Signal Quality Index

5.11.1

BACKGROUND

MLT-3 modulation is used for data transmission in 100BASE-TX and PAM5 modulation is used for data transmission in

1000BASE-T.

Logically, 100BASE-TX (MLT-3) and 1000BASE-T (PAM5) have signal values of {-1, 0, +1} and {-2, -1, 0, +1, +2},

respectively. These logic levels are mapped to slicer reference levels of {-128, 0, 128} for 100BASE-TX and {-128, -64,

0, 64, 128} for 1000BASE-T. The middle points (the compare thresholds) are {-64, 64} for 100BASE-TX and are {-96, -

32, 32, 96} for 1000BASE-T.

Ideally, each receive data sample would be the maximum distance from the compare thresholds, with error values of 0.

But because of noise and imperfection in real applications, the sampled data may be off from its ideal. The closer to the

compare threshold, the worse the signal quality.

The slicer error is a measurement of how far the processed data is off from its ideal location. The largest instantaneous

slicer error for 1000BASE-T is ±32. The largest instantaneous slicer error for 100BASE-TX is ±64.

A higher absolute slicer error means a degraded signal receiving condition.

Note:

The GPIO needs to be enabled and its direction set as an output via the General Purpose IO Enable reg-

ister (GPIO_EN) and the General Purpose IO Direction register (GPIO_DIR). The GPIO Buffer Type (GPI-

O_BUF) field in the General Purpose IO Buffer Type register (GPIO_BUF) also applies.

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