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LAN8804/ZMXC1 Datasheet(PDF) 8 Page - Microchip Technology |
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LAN8804/ZMXC1 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 91 page  LAN8804 DS00003591G-page 8 © 2024 Microchip Technology Inc. and its subsidiaries 2.0 INTRODUCTION 2.1 General Description The LAN8804 is a low-power, quad-port triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical layer transceiver (PHY) that supports transmission and reception of data on standard CAT-5, as well as CAT-5e and CAT-6, Unshielded Twisted Pair (UTP) cables. The LAN8804 supports industry-standard QSGMII (Quad Serial Gigabit Media Independent Interface) providing chip- to-chip connection to four Gigabit Ethernet MACs using a single serialized link (differential pair) in each direction. The LAN8804 reduces board cost and simplifies board layout by using on-chip termination resistors for the line-facing differential pairs. The LAN8804 offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. The LinkMD TDR-based cable diagnostic identifies faulty copper cabling. Integrated loopback functions verify analog and digital data paths. The LAN8804 is available in a 128-pin, RoHS Compliant TQFP package with commercial (0C to +85C) and industrial (-40C to +85C) temperature ranges. An internal block diagram of the LAN8804 is shown in Figure 2-1. FIGURE 2-1: INTERNAL BLOCK DIAGRAM QSGMII Interface MDIO Ethernet Media Interface Port 0 GMII GPHY Hard Macro Tx/Rx Rate Adaptation FIFOs GMII Ethernet Media Interface Port 1 GMII GPHY Hard Macro Tx/Rx Rate Adaptation FIFOs GMII Ethernet Media Interface Port 2 GMII GPHY Hard Macro Tx/Rx Rate Adaptation FIFOs GMII Ethernet Media Interface Port 3 GMII GPHY Hard Macro Tx/Rx Rate Adaptation FIFOs GMII Chip Common Registers PCS1G LEDs PCS1G LEDs PCS1G LEDs PCS1G LEDs 8 LEDs 4 Tx SOF 4 Rx SOF Analog Common Macro Digital Common GMII GMII GMII GMII Customer Temp Monitor XTAL / 25M Ref Clk Reset LDO 125M Ref Clk 25M Clk Out VREG_BYPASS REF_PAD_CLKP/M LAN8804 |
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