LAN8804SLASHZMXC1 datasheet(46/91 Pages) MICROCHIP

46 / 91 page

LAN8804

DS00003591G-page 46

The RX QSGMII Extender uses the K28.1 symbol to locate Port 0, then swaps the K28.1 symbol back to the original

K28.5, before sending the four demultiplexed streams to their RX PCS1G blocks.

QSGMII loopbacks are discussed in Section 5.12.4, "QSGMII Loopback".

5.14 MIIM (MDIO) Interface

The device supports the IEEE 802.3 MII management interface, also known as the Management Data Input/Output

(MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the device. An external

device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details about the

MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification [1].

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (

MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows an external con-

troller to communicate with one or more devices. Each device is assigned a unique PHY address between 0h and

1Fh by the

PHYAD[4:0] strapping pins. Refer to Section 3.3.3, "All PHYs Address (ALLPHYAD)" for additional

information.

• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-

rect access to MMD addresses and registers.

Table 5-6 shows the MII management frame format for the device.

5.14.1

HIGH-SPEED MDIO OPERATION

The MDIO bus can operate at standard speeds up to 2.5 MHz, as well as higher speeds up to 25 MHz. Default register

values enable standard MDIO operation using open-drain MDIO drivers, which is MDIO operation up to 2.5 MHz MDC

frequency with daisy-chained PHYs on the MDIO bus. Due to open-drain drivers, an external 1kΩ pull-up resistor is

required.

Higher speed MDIO operation up to 25 MHz is supportable but requires reconfiguring the device to use push-pull MDIO

drivers, and does not allow daisy-chaining PHYs on the MDIO bus. The reconfiguration process requires initially running

the MDIO bus at 2.5 MHz using open-drain MDIO drivers and the external 1kΩ pull-up resistor. The push-pull MDIO

drivers allow operation up to 25 MHz with the 1kΩ pull-up resistor.

Note:

PHY TX and RX directions are relative to the Ethernet Media Interfaces. QSGMII TX and RX directions are

relative to the QSGMII SerDes interface. So device frames received from the Ethernet Media Interfaces

are processed in RX GPHY and in TX QSGMII blocks.

Note:

If Energy Efficient Ethernet (EEE) is enabled, it is controlled using LPI symbols, which pass transparently

through QSGMII.

Note:

Coma mode has no effect on QSGMII functions.

TABLE 5-6:

MII MANAGEMENT FRAME FORMAT

Preamble Start of

Frame

Read/Write

OP Code

PHY

Address

Bits[4:0]

REG

Address

Bits[4:0]

Data Bits[15:0]

Idle

Read

32 1’s

AAAAA

RRRRR

Z0 DDDDDDDD_DDDDDDDD

Write

32 1’s

AAAAA

RRRRR

DDDDDDDD_DDDDDDDD

Note:

This device may respond to Clause 45 accesses and so must not be mixed with Clause 45 devices on the

same MDIO bus.

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