LAN8804SLASHZMXC1 datasheet(73/91 Pages) MICROCHIP

73 / 91 page

LAN8804

DS00003591G-page 73

6.6.2

POWER SEQUENCE TIMING

This diagram illustrates the device power sequencing requirements.

The recommended power-up sequence is to have the transceiver (

VDDAH, VDDAH_x) and digital I/O (VDDIO,

VDDIO_1) voltages power up before the 1.1V core (VDDCORE, VDDAL_x, VDDTXL_SERDES) voltage. If the 1.1V

core must power up first, the maximum lead time for the 1.1V core voltage with respect to the transceiver and digital

I/O voltages must be 200 μs.

There is no power sequence requirement between transceiver (

VDDAH, VDDAH_x) and digital I/O (VDDIO, VDDIO_1)

power rails.

The power-up waveforms must be monotonic for all supply voltages to the device.

RESET_N must be held asserted following stable voltages for the minimum period specified and if re-asserted, for the

minimum period specified.

The recommended power-down sequence is to have the 1.1V core voltage power-down before powering down the

transceiver and digital I/O voltages.

Before the next power-up cycle, all supply voltages to the device must reach less than 0.4V and there must be a mini-

mum wait time of 150 ms from power-off to power-on.

FIGURE 6-2:

POWER SEQUENCE TIMING INTERNAL REGULATORS

TABLE 6-15: POWER SEQUENCING TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

tvr

Supply voltages rise time (must be monotonic)

—

200

µs

tsr

Stable supply voltages to de-assertion of reset

100

—

trstia

RESET_N input assertion time

—

µs

tscrd

Stable external clock references to de-assertion of reset

—

tpc

Supply voltages cycle off-to-on time

150

—

VDDAL_x,

VDDTXL_SERDES,

VDDCORE

VDDAH, VDDAH_x,

VDDIO, VDDIO_1

tvr

RESET_N

trstia

External Clock Inputs

tscrd

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